On Dec 27, 2007 10:44 PM, aaron lwe <[EMAIL PROTECTED]> wrote: > ron, you're right, it's a dram configuration problem. > after I set the dram clocking control and signal timing > control registers, it worked well after enabling memory > cache. Hmm...these registers have nothing to do when > cache disabled? and they are not mentioned in the > bios porting guide either >
This is a tricky issue that can come up when caching is turned on, since caching does bursts, and that's another point at which any small timing errors will be experienced. That's what happened to you ... I am very glad you fixed it. thanks ron -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
