With the latest microcde update, there's one big problem: size. I
haven't gotten to work yet on the model_f* cpus, but with the model_6xx
cpus, we're way over the size barrier. So, I'd like to propose some
changes to the organization, mostly for the better. The directory
structure, in the end, would look something like this:
cpu/intel/:
/intel_generic/: contains generic intel init code, used by all intel
cpus. Also contains a generic driver, with no microcode updates and
_all_ intel CPU IDs, for using an OS microcode update.
/microcode/: contains all microcode files from the most recent update
(20070907), along with current microcode update code.
/slot_1_p2/: contains CPU IDs and microcode updates for Slot 1 P2s,
P2-based Celerons, and mobile P2/P2-based Celerons
/slot_1_p3/: Same as above, except for P3s, no mobiles
/socket_370/: Same as above, for Socket 370 and mobile CPUs
etc, etc.
Benefits:
* We gain the latest microcode updates and support for every current
Intel CPU, including Core/Core 2 (on an experimental, but it should
work, basis).
* Removal of a bunch of repeated code, no more model_xxx
folders/confusion, just select a socket
Side Effects:
* The end user needs to select between p2 and p3 cpus for slot 1
systems. This may also come up in LGA775-based systems, due to size
constraints
* The code looks somewhat ugly
I've attached intel_init.c, which is the generic intel CPU init, and
slot_1_p2.c, which uses it, so you can see what I'm talking about.
slot_1_p2.c was formerly just slot_1.c, so commented microcode updates
and the appropriate CPU IDs will be removed. Feedback greatly appreciated!
Thanks,
Corey
#include <console/console.h>
#include <device/device.h>
#include <device/device.h>
#include <device/pci.h>
#include <string.h>
#include <cpu/cpu.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
#include <cpu/intel/microcode.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
#ifdef CONFIG_SMP
#if CONFIG_SMP
#include <cpu/intel/hyperthreading.h>
#endif
#endif
struct cpu_device_id cpu_table[];
u32 microcode_updates[];
static void intel_init(device_t dev)
{
/* Turn on L1 caching if we haven't already */
x86_enable_cache();
x86_setup_mtrrs(36);
x86_mtrr_check();
/* Update the microcode */
intel_update_microcode(microcode_updates);
/* Enable the local cpu apics */
setup_lapic();
#ifdef CONFIG_SMP
#if CONFIG_SMP
/* Start up my cpu siblings */
intel_sibling_init(cpu);
#endif
#endif
};
static struct device_operations cpu_dev_ops = {
.init = intel_init,
};
static const struct cpu_driver driver __cpu_driver = {
.ops = &cpu_dev_ops,
.id_table = cpu_table,
};
#include "../intel_generic/intel_init.c"
u32 microcode_updates[] = {
/* WARNING - Intel has a new data structure that has variable length
* microcode update lengths. They are encoded in int 8 and 9. A
* dummy header of nulls must terminate the list.
*/
/* 0x0633 */
#include "../microcode/308-MU163336.inc"
/* 0x0634 */
#include "../microcode/309-MU163437.inc"
/* 0x0650 */
#include "../microcode/146-MU16502e.inc"
#include "../microcode/147-MU16502f.inc"
#include "../microcode/429-MU165040.inc"
#include "../microcode/430-MU165041.inc"
#include "../microcode/433-MU165045.inc"
#include "../microcode/94-MU265019.inc"
/* 0x0651 */
#include "../microcode/434-MU165140.inc"
#include "../microcode/435-MU165141.inc"
#include "../microcode/436-MU165142.inc"
/* 0x0652 */
#include "../microcode/407-MU16522a.inc"
#include "../microcode/409-MU16522c.inc"
#include "../microcode/410-MU16522d.inc"
#include "../microcode/423-MU26522b.inc"
/* 0x0653 */
#include "../microcode/411-MU16530c.inc"
#include "../microcode/412-MU16530d.inc"
#include "../microcode/422-MU26530b.inc"
#include "../microcode/452-MU165310.inc"
/* 0x066a */
#include "../microcode/399-MU166a0b.inc"
#include "../microcode/400-MU166a0c.inc"
#include "../microcode/401-MU166a0d.inc"
#if 0
/* 0x0672 */
#include "../microcode/452-MU165310.inc"
#include "../microcode/540-mu267238.inc"
/* 0x0673 */
#include "../microcode/530-mu16730e.inc"
#include "../microcode/531-mu26732e.inc"
/* 0x0681 */
#include "../microcode/534-MU16810d.inc"
#include "../microcode/535-MU16810e.inc"
#include "../microcode/536-MU16810f.inc"
#include "../microcode/537-MU268110.inc"
#include "../microcode/538-MU168111.inc"
/* 0x0683 */
#include "../microcode/550-MU168307.inc"
#include "../microcode/551-MU168308.inc"
#include "../microcode/727-MU168313.inc"
#include "../microcode/728-MU168314.inc"
#include "../microcode/729-MU268310.inc"
/* 0x0686 */
#include "../microcode/611-MU168607.inc"
#include "../microcode/612-MU168608.inc"
#include "../microcode/615-MU16860a.inc"
#include "../microcode/617-MU16860c.inc"
#include "../microcode/618-MU268602.inc"
#endif
/* Dummy terminator */
0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0,
};
/* Slot 1 CPU IDs. Note that the same ID is sometimes used for Celeron,
* Pentium, and Xeon families, in various packages. This also includes
* Mobile Pentium II and Celeron families */
struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_INTEL, 0x0633 },
{ X86_VENDOR_INTEL, 0x0634 },
{ X86_VENDOR_INTEL, 0x0650 },
{ X86_VENDOR_INTEL, 0x0651 },
{ X86_VENDOR_INTEL, 0x0652 },
{ X86_VENDOR_INTEL, 0x0653 },
{ X86_VENDOR_INTEL, 0x066a },
{ X86_VENDOR_INTEL, 0x0672 },
{ X86_VENDOR_INTEL, 0x0673 },
{ X86_VENDOR_INTEL, 0x0681 },
{ X86_VENDOR_INTEL, 0x0683 },
{ X86_VENDOR_INTEL, 0x0686 },
{ 0, 0 },
};
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