Marc Jones wrote:
ron minnich wrote:
Marc, here are the register dumps.
As a reminder, we seem to have no memory above 1M.
It looks like stage2 has problems. The MSRs are not setup beyond what
stage1 did to allow stage2 to run.
Specificly, geodelx_pci_domain_phase2() is not running.
Can you send your entire output?
Marc
Ron,
I think I am up to the same point you are. It looks like there is a
problem in the device scanning.
void dev_phase2(void) should call geodelx_pci_domain_phase2() for the
southbridge device.
Here is the output. Is this the correct order? It seems strange.
Phase 2: Early setup...
dev_phase2: dev root:
dev_phase2: dev cpus:
dev_phase2: dev device0_0:
dev_phase2: dev southbridge:
dev_phase2: dev domain0:
Phase 2: Done.
I attached my complete output.
Marc
--
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:[EMAIL PROTECTED]
http://www.amd.com/embeddedprocessors
LinuxBIOS-3.0.0 Fri Jan 11 15:53:52 MST 2008 starting...
Choosing fallback boot.
LAR: Attempting to open 'fallback/initram/segment0'.
LAR: Start 0xfffc0000 len 0x40000
LAR: seen member normal/option_table
LAR: seen member normal/stage2/segment0
LAR: seen member normal/stage2/segment1
LAR: seen member normal/initram/segment0
LAR: seen member bootblock
LAR: File not found!
LAR: Run file fallback/initram/segment0 failed: No such file.
Fallback failed. Try normal boot
LAR: Attempting to open 'normal/initram/segment0'.
LAR: Start 0xfffc0000 len 0x40000
LAR: seen member normal/option_table
LAR: seen member normal/stage2/segment0
LAR: seen member normal/stage2/segment1
LAR: seen member normal/initram/segment0
LAR: CHECK normal/initram/segment0 @ 0xfffc49b0
start 0xfffc4a00 len 5564 reallen 5564 compression 0 entry 0x000010ca
loadaddress 0x00000000
Entry point is 0xfffc5aca
pll_reset: read msr 0x4c000014
_MSR GLCP_SYS_RSTPLL (4c000014) value is: 00000398:0000181e
Configuring PLL
LinuxBIOS-3.0.0 Fri Jan 11 15:53:52 MST 2008 starting...
Choosing fallback boot.
LAR: Attempting to open 'fallback/initram/segment0'.
LAR: Start 0xfffc0000 len 0x40000
LAR: seen member normal/option_table
LAR: seen member normal/stage2/segment0
LAR: seen member normal/stage2/segment1
LAR: seen member normal/initram/segment0
LAR: seen member bootblock
LAR: File not found!
LAR: Run file fallback/initram/segment0 failed: No such file.
Fallback failed. Try normal boot
LAR: Attempting to open 'normal/initram/segment0'.
LAR: Start 0xfffc0000 len 0x40000
LAR: seen member normal/option_table
LAR: seen member normal/stage2/segment0
LAR: seen member normal/stage2/segment1
LAR: seen member normal/initram/segment0
LAR: CHECK normal/initram/segment0 @ 0xfffc49b0
start 0xfffc4a00 len 5564 reallen 5564 compression 0 entry 0x000010ca
loadaddress 0x00000000
Entry point is 0xfffc5aca
pll_reset: read msr 0x4c000014
_MSR GLCP_SYS_RSTPLL (4c000014) value is: 00000398:07de001e
Done pll_reset
SMBus WAIT ERROR 13
SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13
Done cpubug fixes
SMBus WAIT ERROR 13
SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13
SMBus WAIT ERROR 13
SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13
========== Check present =======================================================
========== MODBANKS ============================================================
========== FIELDBANKS ==========================================================
========== SPDNUMROWS ==========================================================
========== SPDBANKDENSITY ======================================================
========== BEFORT CTZ ==========================================================
========== TEST DIMM SIZE>8 ====================================================
========== PAGESIZE ============================================================
========== MAXCOLADDR ==========================================================
========== RDMSR CF07 ==========================================================
========== WRMSR CF07 ==========================================================
========== ALL DONE ============================================================
========== Check present =======================================================
SMBus WAIT ERROR 13
SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13
SMBus WAIT ERROR 13
SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13
SMBus WAIT ERROR 13
SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13
SMBus WAIT ERROR 13
SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13
SMBus WAIT ERROR 13
SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13
SMBus WAIT ERROR 13
SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13
SMBus WAIT ERROR 13
SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13
SMBus WAIT ERROR 13
SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13
SMBus WAIT ERROR 13
SMBus READ ERROR: smbus_send_slave_address; device a2SMBus WAIT ERROR 13
DRAM controller init done.
RAM DLL lock
run_file returns with 0
Done RAM init code
========== Disable_car: done wbinvd ============================================
========== disable_car: done ===================================================
LAR: Attempting to open 'normal/stage2/segment0'.
LAR: Start 0xfffc0000 len 0x40000
LAR: seen member normal/option_table
LAR: seen member normal/stage2/segment0
LAR: CHECK normal/stage2/segment0 @ 0xfffc0500
start 0xfffc0550 len 16958 reallen 31776 compression 1 entry 0x00001000
loadaddress 0x00001000
LAR: Compression algorithm #1 used
LAR: Attempting to open 'normal/stage2/segment1'.
LAR: Start 0xfffc0000 len 0x40000
LAR: seen member normal/option_table
LAR: seen member normal/stage2/segment0
LAR: seen member normal/stage2/segment1
LAR: CHECK normal/stage2/segment1 @ 0xfffc4790
start 0xfffc47e0 len 454 reallen 5148 compression 1 entry 0x00001000
loadaddress 0x00009000
LAR: Compression algorithm #1 used
LAR: Attempting to open 'normal/stage2/segment2'.
LAR: Start 0xfffc0000 len 0x40000
LAR: seen member normal/option_table
LAR: seen member normal/stage2/segment0
LAR: seen member normal/stage2/segment1
LAR: seen member normal/initram/segment0
LAR: seen member bootblock
LAR: File not found!
LAR: load_file: No such file 'normal/stage2/segment2'
LAR: load_file_segments: All loaded, entry 0x00001000
Phase 1: Very early setup...
Phase 1: done
Show all devs...
root(Root Device): enabled 1 have_resources 0 initialized 0
cpus: Unknown device path type: 0
cpus(): enabled 1 have_resources 0 initialized 0
device0_0(PCI: 00:01.0): enabled 1 have_resources 0 initialized 0
southbridge(PCI: 00:01.1): enabled 1 have_resources 0 initialized 0
domain0(PCI_DOMAIN: 0000): enabled 1 have_resources 0 initialized 0
Phase 2: Early setup...
dev_phase2: dev root:
dev_phase2: dev cpus:
dev_phase2: dev device0_0:
dev_phase2: dev southbridge:
dev_phase2: dev domain0:
Phase 2: Done.
Show all devs...
root(Root Device): enabled 1 have_resources 0 initialized 0
cpus: Unknown device path type: 0
cpus(): enabled 1 have_resources 0 initialized 0
device0_0(PCI: 00:01.0): enabled 1 have_resources 0 initialized 0
southbridge(PCI: 00:01.1): enabled 1 have_resources 0 initialized 0
domain0(PCI_DOMAIN: 0000): enabled 1 have_resources 0 initialized 0
Phase 3: Enumerating buses...
dev_phase3_scan: scanning root(Root Device)
scan_static_bus for root (Root Device)
cpus: Unknown device path type: 0
cpus() enabled
domain0(PCI_DOMAIN: 0000) enabled
scan_static_bus for root(Root Device) done
dev_phase3_scan: returning 0
Phase 3: Done.
Show all devs...
root(Root Device): enabled 1 have_resources 0 initialized 0
cpus: Unknown device path type: 0
cpus(): enabled 1 have_resources 0 initialized 0
device0_0(PCI: 00:01.0): enabled 1 have_resources 0 initialized 0
southbridge(PCI: 00:01.1): enabled 1 have_resources 0 initialized 0
domain0(PCI_DOMAIN: 0000): enabled 1 have_resources 0 initialized 0
Phase 4: Allocating resources...
Phase 4: Reading resources...
Root Device compute_allocate_io: base: 00000400 size: 00000000 align: 0 gran: 0
read_resources: root(Root Device) read_resources bus 0 link: 0
read_resources: root(Root Device) dtsname cpus have_resources 0 enabled 1
cpus: Unknown device path type: 0
read_resources: cpus() missing phase4_read_resources
read_resources: root(Root Device) dtsname domain0 have_resources 0 enabled 1
read_resources: domain0(PCI_DOMAIN: 0000) missing phase4_read_resources
read_resources: root(Root Device) read_resources bus 0 link: 0 done
Root Device compute_allocate_io: base: 00000400 size: 00000000 align: 0 gran: 0
done
Root Device compute_allocate_mem: base: 00000000 size: 00000000 align: 0 gran: 0
read_resources: root(Root Device) read_resources bus 0 link: 0
read_resources: root(Root Device) dtsname cpus have_resources 0 enabled 1
cpus: Unknown device path type: 0
read_resources: cpus() missing phase4_read_resources
read_resources: root(Root Device) dtsname domain0 have_resources 0 enabled 1
read_resources: domain0(PCI_DOMAIN: 0000) missing phase4_read_resources
read_resources: root(Root Device) read_resources bus 0 link: 0 done
Root Device compute_allocate_mem: base: 00000000 size: 00000000 align: 0 gran:
0 done
Phase 4: Done reading resources.
Phase 4: Setting resources...
Root Device compute_allocate_io: base: 00001000 size: 00000000 align: 0 gran: 0
read_resources: root(Root Device) read_resources bus 0 link: 0
read_resources: root(Root Device) dtsname cpus have_resources 0 enabled 1
cpus: Unknown device path type: 0
read_resources: cpus() missing phase4_read_resources
read_resources: root(Root Device) dtsname domain0 have_resources 0 enabled 1
read_resources: domain0(PCI_DOMAIN: 0000) missing phase4_read_resources
read_resources: root(Root Device) read_resources bus 0 link: 0 done
Root Device compute_allocate_io: base: 00001000 size: 00000000 align: 0 gran: 0
done
Root Device compute_allocate_mem: base: 100000000 size: 00000000 align: 0 gran: 0
read_resources: root(Root Device) read_resources bus 0 link: 0
read_resources: root(Root Device) dtsname cpus have_resources 0 enabled 1
cpus: Unknown device path type: 0
read_resources: cpus() missing phase4_read_resources
read_resources: root(Root Device) dtsname domain0 have_resources 0 enabled 1
read_resources: domain0(PCI_DOMAIN: 0000) missing phase4_read_resources
read_resources: root(Root Device) read_resources bus 0 link: 0 done
Root Device compute_allocate_mem: base: 100000000 size: 00000000 align: 0 gran:
0 done
root(Root Device) assign_resources, bus 0 link: 0
root(Root Device) assign_resources, bus 0 link: 0
Phase 4: Done setting resources.
Phase 4: Done allocating resources.
Show all devs...
root(Root Device): enabled 1 have_resources 0 initialized 0
cpus: Unknown device path type: 0
cpus(): enabled 1 have_resources 0 initialized 0
device0_0(PCI: 00:01.0): enabled 1 have_resources 0 initialized 0
southbridge(PCI: 00:01.1): enabled 1 have_resources 0 initialized 0
domain0(PCI_DOMAIN: 0000): enabled 1 have_resources 0 initialized 0
Phase 5: Enabling resources...
cpus: Unknown device path type: 0
dev_phase5: cpus() missing ops
dev_phase5: domain0(PCI_DOMAIN: 0000) missing ops
Phase 5: Done.
Show all devs...
root(Root Device): enabled 1 have_resources 0 initialized 0
cpus: Unknown device path type: 0
cpus(): enabled 1 have_resources 0 initialized 0
device0_0(PCI: 00:01.0): enabled 1 have_resources 0 initialized 0
southbridge(PCI: 00:01.1): enabled 1 have_resources 0 initialized 0
domain0(PCI_DOMAIN: 0000): enabled 1 have_resources 0 initialized 0
Phase 6: Initializing devices...
Phase 6: Root Device init.
Phase 6: Devices initialized.
Show all devs...
root(Root Device): enabled 1 have_resources 0 initialized 1
cpus: Unknown device path type: 0
cpus(): enabled 1 have_resources 0 initialized 0
device0_0(PCI: 00:01.0): enabled 1 have_resources 0 initialized 0
southbridge(PCI: 00:01.1): enabled 1 have_resources 0 initialized 0
domain0(PCI_DOMAIN: 0000): enabled 1 have_resources 0 initialized 0
LAR: Attempting to open 'normal/option_table'.
LAR: Start 0xfffc0000 len 0x3c000
LAR: seen member normal/option_table
LAR: CHECK normal/option_table @ 0xfffc0000
start 0xfffc0050 len 1200 reallen 1200 compression 0 entry 0x00000000
loadaddress 0x00000000
search_global_resources: mask 4200 type 4200
search_global_resources: dev root, have_resources 0 #resources 2
search_global_resources: dev cpus, have_resources 0 #resources 0
search_global_resources: dev device0_0, have_resources 0 #resources 0
search_global_resources: dev southbridge, have_resources 0 #resources 0
search_global_resources: dev domain0, have_resources 0 #resources 0
lb_cleanup_memory_ranges: # entries 0
lb_memory_range: start 0x0 size 0x500
lb_cleanup_memory_ranges: # entries 1
#0: base 0x00000000 size 0x500
lb_memory_range: start 0xf0000 size 0x0
lb_cleanup_memory_ranges: # entries 2
#0: base 0x00000000 size 0x500
#1: base 0x000f0000 size 0x0
Wrote LinuxBIOS table at: 0x00000500 - 0x00000b60 checksum 2d70
Show all devs...
root(Root Device): enabled 1 have_resources 0 initialized 1
cpus: Unknown device path type: 0
cpus(): enabled 1 have_resources 0 initialized 0
device0_0(PCI: 00:01.0): enabled 1 have_resources 0 initialized 0
southbridge(PCI: 00:01.1): enabled 1 have_resources 0 initialized 0
domain0(PCI_DOMAIN: 0000): enabled 1 have_resources 0 initialized 0
Stage2 code done.
LAR: Attempting to open 'normal/payload'.
LAR: Start 0xfffc0000 len 0x40000
LAR: seen member normal/option_table
LAR: seen member normal/stage2/segment0
LAR: seen member normal/stage2/segment1
LAR: seen member normal/initram/segment0
LAR: seen member bootblock
LAR: File not found!
LAR: Attempting to open 'normal/payload/segment0'.
LAR: Start 0xfffc0000 len 0x40000
LAR: seen member normal/option_table
LAR: seen member normal/stage2/segment0
LAR: seen member normal/stage2/segment1
LAR: seen member normal/initram/segment0
LAR: seen member bootblock
LAR: File not found!
LAR: load_file: No such file 'normal/payload/segment0'
LAR: load_file_segments: Failed for normal/payload
FATAL: No usable payload found.
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