This causes PIII/800 systems to hang. I'm beginning to think that for
these more tricky optimizations I'd like to do it when Linux hits runlevel
3. This will ensure that we can always get to runlevel 1, so that if there
is a problem we can recover in linux.
More detail:
For every chipset, I would like the chipset to have 'guaranteed' timing.
This timing should stay that way until Linux runlevel 1. Then, as part of
the transition to Runlevel 3, a script or a smart program could set bits
that improve performance.
There are a lot of advantages to this idea.
1) Even if you get the performance bits wrong, you can always get the
machine up to Linux. It's much easier to debug this way.
2) You can test new enhancements, and not worry that the machine will
simply go comatose. We've seen this with regular BIOS, where the only
option once you set something wrong is to open the case and clear CMOS.
Imagine doing this to 1024 machines.
Comments?
ron
----
Here's the patch I am applying to 630_regs.inc for now. This is now
committed.
cvs server: Diffing src/northsouthbridge/sis/630
Index: src/northsouthbridge/sis/630/630_regs.inc
===================================================================
RCS file:
/cvsroot/freebios/freebios/src/northsouthbridge/sis/630/630_regs.inc,vretrieving
revision 1.4
diff -r1.4 630_regs.inc
41a42
> #ifdef ENABLE_SIS630_CPU_PIPELINE
42a44,46
> #else
> .byte 0x50, 0x9C #
> #endif
103c107
< northbridge_init_table_end:
\ No newline at end of file
---
> northbridge_init_table_end:
I am committing this one.
