Jeremy Jackson <[EMAIL PROTECTED]> writes:
> "Eric W. Biederman" wrote:
>
> > In:
> >
> Intel_Architecture_Software_Developers_Manual,_Volume_3:_System_Programming.pdf
>
> > aka
> > 24319202.pdf
> >
> > on page: (335) aka 9-11
> >
> > It describes caching behavior when CD & NW are set but there are valid
> > cache blocks in the cache. Basically it says in such a situation no cache
> blocks
>
> > are played with but the existing cache blocks are used.
> >
> > So with the proper prefill algorithm doing the memory init from C code
> > should be possible. My problem: filling the Level-1 Data cache is
> > simple (so C doing memory init in C will happen). Filling the Level-1
> > Instruction cache, is this possible without executing the
> > instructions?
>
> >
> >
> > Eric
>
> I think I'm coming in on the middle of this discussion, (or maybe just
> didn't pay attention until now - doh ), can you remind me of the
> prerequisites for meminit in C? Do you just need a stack (D cache)
> or do you NEED I cache too?
There are actually two problems being able to do memory init from cache solve.
1) The code is much simpler in C and for that all I need is a stack from
the D cache.
2) If you can move some code into the I-cache you can more easily use
the DOC millenium for a boot ROM, as you can copy the code out of
it. Plus you get a bit CPU speed up if you aren't always running
out of uncacheable RAM, so timings should be more consistent.
> I will go read the spec sheet mentioned now, but off the top of my head,
> isn't the L2 cache unified (not partitioned I/D)? if so, couldn't you
> enable the L2, write code into "memory", then when the L1 I cache
> goes to read "memory", it will pull in the code?
The L2 cache is still unified but there are some interesting issues
with initializing L2 cache. If initializing L2 cache is simple enough
I don't have any problems, but if it is a royal pain I would like to
put that off for another day.
Eric
