Ollie Lho <[EMAIL PROTECTED]> writes:
> "Eric W. Biederman" wrote:
> >
> >
> > Another idea is to break linuxBIOS into the phases:
> > phase1 turn on the RAM
> > initialize the hardware
> > phase2 initialize the RAM with new kernel & assorted data structures.
> >
> > I like this because you can use the normal printk while turning the
> > RAM on.
> >
>
> It is impossible to init RAM twice on SiS 630 and friends. I do think
> the same thing happens for other chipsets.
I wasn't think that. What I was thinking was to initialize the L1 D-cache,
and lock the cache block in place. And to use those locked cache blocks
as the stack, bss, data area while turning ram on, possibly while
doing other things. The cache blocks would be logically caching an
address where there are no I/O devices or memory.
Locking blocks in the cache is documented to work via Intel, so it is only
a small risk, of initializing the cache.
Eric.
