[EMAIL PROTECTED] writes:
> On 21 Mar, To: [EMAIL PROTECTED] wrote:
> > I currenlty need to load things into SDRAM from a paged flash that is
> > larger than the 1Meg window available. To survive this, I currently
> > put a copy of linuxbios at the top of every page.
>
> ...I didn't think of what might be the simplest and obvious solution.
>
> Play with the southbridge to copy the bios to SDRAM in the same space
> that the bios normally resides. I.E. Normal bios SDRAM shadowing. I
> think I can set things up so that reads come from the flash, writes go
> to the SDRAM and then switch so that reads come from the SDRAM and do
> an "in-place" copy. No address translations needed and once it is done
> I am free to page my flash all I want and access it in the top Meg of
> the address space.
>
> Does anyone know if I am wrong about this?
You are close. You need to play with the northbridge. For the 440x
series of chipset it is the PAM Programable Attribute Map registers,
that you need to manipulate.
I'm thinking this might be a complimentary idea of running directly
out of cache, and setting up ram. But I don't think the gymnastics
art possible to run out of rom, then cache, then ram all at the same
address.
Eric
