Ollie Lho <[EMAIL PROTECTED]> writes:
> "Eric W. Biederman" wrote:
> >
> > Well I'm convinced the SIS730 chipset is a whole different animal
> > then the AMD760 chipset. On the AMD760 chipset I can't even access
> > memory without setting processor specific registers that Ollie's code
> > doesn't even touch.
> >
> > The EV6 bus has both memory mapped memory cycles and memory mapped i/o
> > cycles, and until I find out otherwise I'm convinced Ollies code is
> > doing all memory mapped i/o cycles to access memory on the SIS730
> > chipset. Which probably accounts for the weird speed anomolies.
> >
>
> I agree. There are many K7 specific MSR which is about S2K (EV6 bus ??)
The alpha 21264 processor is also known as the EV6.
The Socket 2000 stuff expands on what was originally developed for the
alpha with some standard location of i/o devices. This allows the
athlon to default to the right memory addresses for i/o space for example.
> that I did not program at all. The SiS730 code was done in a hurry to be
> showed off in Extreme Linux and after the conference I was busy doing
> 550 stuff.
>
> Does anyone has more idea about these MRS better than me (no idea)
> ??
I very much want to comment on this. But as the only source I have
for detailing which MSR exist I can't give details.
However if you run that program I sent out a while ago. (An exercise
from one of my programming classes years ago). It is obvious that
without setting up some athlon MSR's you get very bad cache
performance.
Eric
