Hello, Since it takes time to get DoC Mil, I was trying to load linux.bin.gz from ethernet using etherboot command. But, it does not work so far while etherboot works.
Log files go like these: >> LinuxBIOS starting... >> Ram Initialize? >> before mainLinuxBIOS booting... >> Finding PCI configuration type. >> PCI: Using configuration type 1 >> handle_superio start, s 00000000 nsuperio 1 s->super bfffffe7 >> handle_superio Pass 0, check #0, s 0000f4c0 s->super 00010918 >> handle_superio: Pass 0, Superio SiS 950 >> handle_superio port 0x0, defaultport 0x2e >> handle_superio Using port 0x2e >> handle_superio Pass 0, done #0 >> handle_superio done >> Scanning PCI bus...PCI: pci_scan_bus for bus 0 >> pci_get_sizedev_fn 0x0, register 1, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0x0, register 2, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0x0, register 3, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0x0, register 4, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0x0, register 5, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> PCI: 00:00 [1039/0630] >> pci_get_sizedev_fn 0x1, register 5, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> PCI: 00:01 [1039/5513] >> pci_get_sizedev_fn 0x8, register 0, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0x8, register 1, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0x8, register 2, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0x8, register 3, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0x8, register 4, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0x8, register 5, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> PCI: 00:08 [1039/0008] >> pci_get_sizedev_fn 0x9, register 2, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0x9, register 3, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0x9, register 4, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0x9, register 5, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> PCI: 00:09 [1039/0900] >> pci_get_sizedev_fn 0xa, register 1, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0xa, register 2, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0xa, register 3, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0xa, register 4, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0xa, register 5, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> PCI: 00:0a [1039/7001] >> pci_get_sizedev_fn 0xb, register 1, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0xb, register 2, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0xb, register 3, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0xb, register 4, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0xb, register 5, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> PCI: 00:0b [1039/7001] >> pci_get_sizedev_fn 0xc, register 2, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0xc, register 3, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0xc, register 4, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0xc, register 5, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> PCI: 00:0c [1039/7018] >> pci_get_sizedev_fn 0xe, register 2, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0xe, register 3, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0xe, register 4, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0xe, register 5, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> PCI: 00:0e [1039/7013] >> pci_get_sizedev_fn 0x10, register 0, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0x10, register 1, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> PCI: 00:10 [1039/0001] >> pci_get_sizedev_fn 0x78, register 1, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0x78, register 2, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0x78, register 3, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0x78, register 4, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0x78, register 5, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> PCI: 00:78 [13f6/0111] >> pci_get_sizedev_fn 0x79, register 1, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0x79, register 2, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0x79, register 3, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0x79, register 4, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0x79, register 5, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> PCI: 00:79 [13f6/0211] >> PCI: pci_scan_bus for bus 1 >> pci_get_sizedev_fn 0x0, register 3, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0x0, register 4, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> pci_get_sizedev_fn 0x0, register 5, read-only SO, ignoring it >> addr was 0x0, size was 0x0 >> PCI: 01:00 [1039/6300] >> PCI: pci_scan_bus returning with max=01 >> PCI: pci_scan_bus returning with max=01 >> done >> totalram: 248M >> Initializing CPU #0 >> Updating microcode >> microcode_info: sig = 0x00000686 pf=0x00000010 rev = 0x00000000 >> Enabling cache... >> Setting variable MTRR 0, base: 0MB, range: 256MB, type: WB >> Setting variable MTRR 1, base: 248MB, range: 8MB, type: UC >> done. >> >> Max cpuid index : 2 >> Vendor ID : GenuineIntel >> Processor Type : 0x00 >> Processor Family : 0x06 >> Processor Model : 0x08 >> Processor Mask : 0x00 >> Processor Stepping : 0x06 >> Feature flags : 0x0383fbff >> >> Cache/TLB descriptor values: 1 reads required >> Desc 0x01 : Instr TLB: 4KB pages, 4-way set assoc, 32 entries >> Desc 0x02 : Instr TLB: 4MB pages, fully assoc, 2 entries >> Desc 0x03 : Data TLB: 4KB pages, 4-way set assoc, 64 entries >> Desc 0x00 : null >> Desc 0x00 : null >> Desc 0x00 : null >> Desc 0x00 : null >> Desc 0x00 : null >> Desc 0x00 : null >> Desc 0x00 : null >> Desc 0x00 : null >> Desc 0x41 : L2 Unified cache: 128K bytes, 4-way set assoc, 32 byte line size >> Desc 0x08 : Inst cache: 16K bytes, 4-way set assoc, 32 byte line size >> Desc 0x04 : Data TLB: 4MB pages, 4-way set assoc, 8 entries >> Desc 0x0c : Data cache: 16K bytes, 2-way or 4-way set assoc, 32 byte line size >> >> >> >> MTRR check >> Fixed MTRRs : Enabled >> Variable MTRRs: Enabled >> >> Configuring L2 cache...CPU signature of 680 so no L2 cache configuration >> Enable Cache >> done. >> Disabling local apic...done. >> CPU #0 Initialized >> Allocating PCI resources...COMPUTE_ALLOCATE: do IO >> compute_allocate_io: base 0x1000 >> compute_allocate_io: base 0x1000 >> Running VGA fix... >> DEVIO: Bus 0x1, devfn 0x0, reg 0x2: iosize 0x80 >> rounded size 128 base 0x1000 >> -->set base to 0x1000 >> BUS 1: set iolimit to 0x1fff >> BUSIO: done Bridge Bus 0x1, iobase now 0x2000 >> DEVIO: Bus 0x0, devfn 0x1, reg 0x0: iosize 0x4 >> rounded size 16 base 0x2000 >> -->set base to 0x2000 >> DEVIO: Bus 0x0, devfn 0x1, reg 0x1: iosize 0x4 >> rounded size 16 base 0x2010 >> -->set base to 0x2010 >> DEVIO: Bus 0x0, devfn 0x1, reg 0x2: iosize 0x4 >> rounded size 16 base 0x2020 >> -->set base to 0x2020 >> DEVIO: Bus 0x0, devfn 0x1, reg 0x3: iosize 0x4 >> rounded size 16 base 0x2030 >> -->set base to 0x2030 >> DEVIO: Bus 0x0, devfn 0x1, reg 0x4: iosize 0x10 >> rounded size 16 base 0x2040 >> -->set base to 0x2040 >> DEVIO: Bus 0x0, devfn 0x9, reg 0x0: iosize 0x100 >> rounded size 256 base 0x2100 >> -->set base to 0x2100 >> DEVIO: Bus 0x0, devfn 0xc, reg 0x0: iosize 0x100 >> rounded size 256 base 0x2200 >> -->set base to 0x2200 >> DEVIO: Bus 0x0, devfn 0xe, reg 0x0: iosize 0x100 >> rounded size 256 base 0x2300 >> -->set base to 0x2300 >> DEVIO: Bus 0x0, devfn 0xe, reg 0x1: iosize 0x80 >> rounded size 128 base 0x2400 >> -->set base to 0x2400 >> DEVIO: Bus 0x0, devfn 0x78, reg 0x0: iosize 0x100 >> rounded size 256 base 0x2500 >> -->set base to 0x2500 >> DEVIO: Bus 0x0, devfn 0x79, reg 0x0: iosize 0x40 >> rounded size 64 base 0x2600 >> -->set base to 0x2600 >> BUS 0: set iolimit to 0x2fff >> COMPUTE_ALLOCATE: do MEM >> compute_allocate_mem: base 0x80000000 >> compute_allocate_mem: base 0x80000000 >> DEVMEM: Bus 0x1, devfn 0x0, reg 0x1: memsize 0x20000 >> -->set base to 0x80000000 >> BUS 1: set memlimit to 0x800fffff >> BUSMEM: Bridge Bus 0x1,membase now 0x80100000 >> DEVMEM: Bus 0x0, devfn 0x0, reg 0x0: memsize 0x4000000 >> -->set base to 0x84000000 >> DEVMEM: Bus 0x0, devfn 0x9, reg 0x1: memsize 0x1000 >> -->set base to 0x88000000 >> DEVMEM: Bus 0x0, devfn 0xa, reg 0x0: memsize 0x1000 >> -->set base to 0x88001000 >> DEVMEM: Bus 0x0, devfn 0xb, reg 0x0: memsize 0x1000 >> -->set base to 0x88002000 >> DEVMEM: Bus 0x0, devfn 0xc, reg 0x1: memsize 0x1000 >> -->set base to 0x88003000 >> BUS 0: set memlimit to 0x880fffff >> COMPUTE_ALLOCATE: do PREFMEM >> Compute_allocate_prefmem: base 0x88100000 >> Compute_allocate_prefmem: base 0x88100000 >> DEVPREFMEM: Bus 0x1, devfn 0x0, reg 0x0: prefmemsize 0x8000000 >> -->set base to 0x90000000 >> BUS 1: set prefmemlimit to 0x97ffffff >> BUSPREFMEM: Bridge Bus 0x1, prefmem base now 0x98000000 >> BUS 0: set prefmemlimit to 0x97ffffff >> ASSIGN RESOURCES, bus 0 >> Bus 0x0 Child Bus 1 iobase to 0x1000 iolimit 0x1fff >> Bus 0x0 Child Bus 1 membase to 0x80000000 memlimit 0x800fffff >> Bus 0x0 Child Bus 1 prefmembase to 0x88100000 prefmemlimit 0x97ffffff >> ASSIGN RESOURCES, bus 1 >> Bus 0x1 devfn 0x0 reg 0x0 base to 0x90000000 >> Bus 0x1 devfn 0x0 reg 0x1 base to 0x80000000 >> Bus 0x1 devfn 0x0 reg 0x2 base to 0x1001 >> Bus 0x0 devfn 0x0 reg 0x0 base to 0x84000000 >> Bus 0x0 devfn 0x1 reg 0x0 base to 0x2001 >> Bus 0x0 devfn 0x1 reg 0x1 base to 0x2011 >> Bus 0x0 devfn 0x1 reg 0x2 base to 0x2021 >> Bus 0x0 devfn 0x1 reg 0x3 base to 0x2031 >> Bus 0x0 devfn 0x1 reg 0x4 base to 0x2041 >> Bus 0x0 devfn 0x9 reg 0x0 base to 0x2101 >> Bus 0x0 devfn 0x9 reg 0x1 base to 0x88000000 >> Bus 0x0 devfn 0xa reg 0x0 base to 0x88001000 >> Bus 0x0 devfn 0xb reg 0x0 base to 0x88002000 >> Bus 0x0 devfn 0xc reg 0x0 base to 0x2201 >> Bus 0x0 devfn 0xc reg 0x1 base to 0x88003000 >> Bus 0x0 devfn 0xe reg 0x0 base to 0x2301 >> Bus 0x0 devfn 0xe reg 0x1 base to 0x2401 >> Bus 0x0 devfn 0x78 reg 0x0 base to 0x2501 >> Bus 0x0 devfn 0x79 reg 0x0 base to 0x2601 >> done. >> Enabling PCI resourcess...DEV Set command bus 0x00 devfn 0x00 to 0x07 >> DEV Set command bus 0x00 devfn 0x01 to 0x01 >> DEV Set command bus 0x00 devfn 0x08 to 0x0c >> DEV Set command bus 0x00 devfn 0x09 to 0x03 >> DEV Set command bus 0x00 devfn 0x0a to 0x02 >> DEV Set command bus 0x00 devfn 0x0b to 0x02 >> DEV Set command bus 0x00 devfn 0x0c to 0x03 >> DEV Set command bus 0x00 devfn 0x0e to 0x01 >> DEV Set command bus 0x00 devfn 0x10 to 0x27 >> DEV Set command bus 0x00 devfn 0x78 to 0x81 >> DEV Set command bus 0x00 devfn 0x79 to 0x01 >> DEV Set command bus 0x01 devfn 0x00 to 0x03 >> done. >> Enabled in SIS 503 regs 0x40 and 0x45 >> Now try to turn off shadow >> handle_superio start, s 0003e000 nsuperio 1 s->super 00000000 >> handle_superio Pass 1, check #0, s 0000f4c0 s->super 00010918 >> handle_superio: Pass 1, Superio SiS 950 >> handle_superio port 0x2e, defaultport 0x2e >> handle_superio Using port 0x2e >> handle_superio Pass 1, done #0 >> handle_superio done >> Zeroing PCI IRQ settings...done. >> Winfast 6300 (and similar)...Remapping IRQ on southbridge for OLD_KERNEL_HACK >> acpibase was 0x5000 >> acpibase is 0xc000 >> acpi enable reg was 0x33 >> acpi enable reg after set is 0xb3 >> acpi status: word at 0x56 is 0x0 >> acpi status: byte at 0x4b is 0x0 >> acpibase + 0x56 is 0x40 >> acpi disable reg after set is 0x33 >> Entering the initregs process >> Southbridge fixup done for SIS 503 >> handle_superio start, s 0003e000 nsuperio 1 s->super 00000000 >> handle_superio Pass 2, check #0, s 0000f4c0 s->super 00010918 >> handle_superio: Pass 2, Superio SiS 950 >> handle_superio port 0x2e, defaultport 0x2e >> handle_superio Using port 0x2e >> Call finishup >> handle_superio Pass 2, done #0 >> handle_superio done >> Copying IRQ routing tables...done. >> Wrote linuxbios table at: 00000500 - 00000518 >> Jumping to linuxbiosmain()... >> >> Welcome to start32, the open sourced starter. >> This space will eventually hold more diagnostic information. >> >> January 2000, James Hendricks, Dale Webster, and Ron Minnich. >> Version 0.1 >> >> >> sis900_probe: MAC addr 00:26:02:40:80:2f at ioaddr 2100 >> sis900_probe: Vendor:1039 Device:0900 >> sis900_probe: No MII transceivers found! >> netboot_init : sis900_probe = 0000 >> doing rarp: And for etherboot: >> Boot from (N)etwork or from (L)ocal? N >> Found SIS900 at 0xde00, ROM address 0xff00 >> Probing...[SIS900] >> sis900_probe: MAC addr 00:00:00:00:00:00 at ioaddr 0XDE00 >> sis900_probe: Vendor:0X1039 Device:0X0900 >> sis900_probe: SiS 900 Internal MII PHY transceiver found at address 1. >> sis900_probe: Using SiS 900 Internal MII PHY as default >> sis900_read_mode: Media Link On 10mbps half-duplex >> Searching for server (RARP)... >> Me: 192.168.0.14, Server: 192.168.0.11 >> Loading 192.168.0.11:/tftpboot/kernel.192.168.0.14 .TFTP error 1 (File not found) >> Unable to load file. >> <sleep> >> <abort> I am using the same 1M bit Flash ROM for both etherboot and linuxbios using first 64kB for first and last 64kB for last flashing on the netcard to avoid hotflash. Mac Addr of 00:00:00:00:00:00 seems is bogus but is correnct one since somehow I wiped out the address as warned by PCCHIPS manual that it would happen when flash and cmos clear happen same time. Also I found that sis900.c files are the same in both in linuxbios and etherboot. Thanks in Advacne. Regards, Kei.
