Ok ... well .. I'll live with it .. :-) Thanks Ollie ...
----- Original Message -----
>From: "Ollie Lho" <[EMAIL PROTECTED]>
>To: "Ian" <[EMAIL PROTECTED]>
>Subject: Re: memory and stuffs
>Date: Fri, 22 Feb 2002 09:07:38 +0800
>
> Ian wrote:
>
> > This is the thing I find *really* frustrating .... the SPD spec has some pretty
>diagrams
> > that explain the read and write operations ... and Figure 10 on page 10 of 28
>appears
> > to line up with line line 70 of 350 of this morning's
>northsouthbridge/sis/630/ipl.S
> >
> > Intel: EEPROM Sequential Read Operation: address "1 0 1 0 A2 A1 A0 1"
> > SIS: movw $0x04a1, %ax # SPD is on SMBUS Address 1010 xyz1
> > # where xyz are
>DIMM Slot Number
> >
> > Cool ... but where does it say, anywhere in the SPD Spec, that the SPD address
scheme
> > has *anything* to do with either the SMBus or the I2C ??
> >
>
>
> The SPD spec does not say SMBus nor I2C. It actually defines the
> protocol itself. It happens that the protocol is identical to
> SMBus (on purpose ??) and main board manufacture route the
> SMBus to the DIMM.
>
>
> > Where are you guys getting this missing information? There seems to be something
> > underlying that threads these standards together, that I just can't find / touch
>... ??
> >
>
>
> It seem that every body in PC chipset/mainboard business knows this. I
> don't know if this is defined in any spec.
>
> Ollie
>
>
>
