On Wed, 2002-04-24 at 10:28, Ronald G Minnich wrote: > Richard, what we did in debugging the 430tx was to first figure out how > the normal bios set things, bit for bit. Then, in the .inc for linuxbios, > everytime we set bits in the DRAM control, we dumped the entire > northbridge register set. There is code to do this in > src/ram/dump_northbridge.inc >
It would be nice if someone actually had instructions on setting up a chipset instead of just reverse engineering things. Intel doesn't document what you need to do, although it has posted some binaries for use in embedded BX systems. (And our hw guys have trouble getting info out of Intel even after signing nondisclosures.) I've got a 440BX going, but apparently you don't initialize a 430TX the same way. 1. For my BX BIOS, and for the commericial BIOS I ran though the ICE, multiple dram rows (must?) get initialized simultaneously. For every SDRAM command issued by reading address n, address next_row_boundary+n also gets read. For the TX, commercial BIOS and LinuxBIOS (must?) do one row at a time. 2. The BX does memory reads for the SDRAM commands; the 430TX/raminit.inc uses writes (although commercial BIOS does reads). 3. 430TX/raminit.inc programs the DRB regs in reverse order, the comment says per Intel errata, but I cannot find that errata. 4. The SDRAM chip spec says that A10 must be high for the precharge all command, and in order for my BX init to work, I had to do a read from address 0x2000. I guess CPU A13 maps to MA10 for our particular configuration. The TX data sheet suggests that CPU A11 might be appropriate, but LinuxBIOS & commercial BIOS code simply use address 0 for all SDRAM commands except MRCE. 5. For reliable BX/memtest86 operation, misc drive strength settings had to be just so. Mere SDRAM fill/verify did not reveal any errors. Fortunately the TX doesn't have these settings.
