Hello,
this patch sets 8111NIC's mac. The 48-bit mac address is saved in OEM ROM,
in nic_init() the driver gets the mac address through register oem_mac_offset,
and copy it to 8111NIC's PADR register.
diff -Nur freebios2-20050305-0000-orig/src/southbridge/amd/amd8111/amd8111_nic.c
freebios2-20050305-0000/src/southbridge/amd/amd8111/amd8111_nic.c
--- freebios2-20050305-0000-orig/src/southbridge/amd/amd8111/amd8111_nic.c
2004-10-21
18:44:04.000000000 +0800
+++ freebios2-20050305-0000/src/southbridge/amd/amd8111/amd8111_nic.c
2005-03-31
12:50:56.000000000 +0800
@@ -6,20 +6,99 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
+#include <delay.h>
#include "amd8111.h"
+#undef writel
+#undef writeb
+#define writel(val,addr) (*(volatile uint32_t *)(addr) = (val))
+#define writeb(val,addr) (*(volatile uint8_t *)(addr) = (val))
+#define CMD3 0x54
+#define PADR 0x160
+
+typedef enum {
+ VAL3 = (1 << 31), /* VAL bit for byte 3 */
+ VAL2 = (1 << 23), /* VAL bit for byte 2 */
+ VAL1 = (1 << 15), /* VAL bit for byte 1 */
+ VAL0 = (1 << 7), /* VAL bit for byte 0 */
+}VAL_BITS;
+
+typedef enum {
+ /* VAL3 */
+ ASF_INIT_DONE_ALIAS = (1 << 29),
+ /* VAL2 */
+ JUMBO = (1 << 21),
+ VSIZE = (1 << 20),
+ VLONLY = (1 << 19),
+ VL_TAG_DEL = (1 << 18),
+ /* VAL1 */
+ EN_PMGR = (1 << 14),
+ INTLEVEL = (1 << 13),
+ FORCE_FULL_DUPLEX = (1 << 12),
+ FORCE_LINK_STATUS = (1 << 11),
+ APEP = (1 << 10),
+ MPPLBA = (1 << 9),
+ /* VAL0 */
+ RESET_PHY_PULSE = (1 << 2),
+ RESET_PHY = (1 << 1),
+ PHY_RST_POL = (1 << 0),
+}CMD3_BITS;
+
+static void nic_init(struct device *dev)
+{
+ struct southbridge_amd_amd8111_config *conf;
+ struct resource *resource;
+ void *mmio;
+ unsigned char *oem_mac_addr;
+ int i;
+
+ conf = dev->chip_info;
+ resource = find_resource(dev, PCI_BASE_ADDRESS_0);
+ mmio = (void *)(unsigned long)resource->base;
+
+ /* Hard Reset PHY */
+ printk_debug("Reseting PHY... ");
+ if (conf->phy_lowreset) {
+ writel(VAL0 | PHY_RST_POL | RESET_PHY , mmio + CMD3);
+ } else {
+ writel(VAL0 | RESET_PHY, mmio + CMD3);
+ }
+ mdelay(15);
+ writel(RESET_PHY, mmio + CMD3);
+ printk_debug("Done\n");
+
+ /* Set MAC address */
+ printk_debug("Mac Addr ");
+ oem_mac_addr = (unsigned char *)(ROM_OEM_START + conf->oem_mac_offset);
+ for (i = 0; i < 6; i++) {
+ printk_debug("%02X%c", oem_mac_addr[i], i == 5 ? '\n' : ':');
+ writeb(oem_mac_addr[i], mmio + PADR + i);
+ }
+}
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+ pci_write_config32(dev, 0xc8,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+ .set_subsystem = lpci_set_subsystem,
+};
+
static struct device_operations nic_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .enable = amd8111_enable,
- .init = 0,
+ .init = nic_init,
.scan_bus = 0,
+ .enable = amd8111_enable,
+ .ops_pci = &lops_pci,
};
static struct pci_driver nic_driver __pci_driver = {
.ops = &nic_ops,
.vendor = PCI_VENDOR_ID_AMD,
- .device = 0x7462,
+ .device = PCI_DEVICE_ID_AMD_8111_NIC,
};
diff -Nur freebios2-20050305-0000-orig/src/southbridge/amd/amd8111/chip.h
freebios2-20050305-0000/src/southbridge/amd/amd8111/chip.h
--- freebios2-20050305-0000-orig/src/southbridge/amd/amd8111/chip.h
2004-10-21
18:44:04.000000000 +0800
+++ freebios2-20050305-0000/src/southbridge/amd/amd8111/chip.h 2005-03-31
12:49:32.000000000 +0800
@@ -5,6 +5,8 @@
{
unsigned int ide0_enable : 1;
unsigned int ide1_enable : 1;
+ unsigned int phy_lowreset : 1;
+ unsigned long oem_mac_offset;
};
struct chip_operations;
--
Liu Tao
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