On Mon, Jun 20, 2005 at 03:44:39PM +0400, Anton Borisov wrote:
> On Mon, 20 Jun 2005 12:32:33 +0100
> Jonathan McDowell <[EMAIL PROTECTED]> wrote:
> > How much memory is on your board? I think the RAM detection stuff is
>
> 256 MB of RAM.
>
> > wrong and that's possibly causing FILO problems; from your
> > minicom.capped2.bz2:
> >
> > I would set ram size to 0x3fc000 Kbytes
>
> Should I learn about a new option inside Config.filo.lb?
No, that's in your log output; from line 223 in vt8623/northbridge.c
> > I've got a list of chipset registers the Award BIOS seems to twiddle, so
> > I might add those to the enable_mainboard function to see if that at
> > least gets us further.
>
> Well, this could help. Can you attach it?
I've attached a modified src/mainboard/via/epia-m/auto.c which sets all
the chipset registers from the Award table I extracted. I don't know if
it'll help or not though.
>I don't remember but it seems to me I've seen somewhere the CMOS map
>according to each LB decides which image to load "Normal" or
>"Fallback". Am I right?
I /think/ so; see do_normal_boot in src/pc80/mc146818rtc_early.c
J.
--
/-\ | 101 things you can't have too much
|@/ Debian GNU/Linux Developer | of : 39 - silver bullets.
\- |
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#if 0
#include <cpu/x86/lapic.h>
#endif
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "northbridge/via/vt8623/raminit.h"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
/*
*/
void udelay(int usecs)
{
int i;
for(i = 0; i < usecs; i++)
outb(i&0xff, 0x80);
}
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "debug.c"
#include "southbridge/via/vt8235/vt8235_early_smbus.c"
#include "southbridge/via/vt8235/vt8235_early_serial.c"
static void memreset_setup(void)
{
}
/*
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
*/
static inline int spd_read_byte(unsigned device, unsigned address)
{
unsigned char c;
c = smbus_read_byte(device, address);
return c;
}
#include "northbridge/via/vt8623/raminit.c"
#define SET_CHIPSET_REG(DEV, REG, MASK, VALUE) \
v = pci_read_config8(DEV, REG); \
v &= ~(MASK); \
v |= VALUE; \
pci_write_config8(DEV, REG, v);
/*
#include "sdram/generic_sdram.c"
*/
static void enable_mainboard_devices(void)
{
device_t dev;
uint16_t r, c;
uint8_t v;
/*
* Fixups from Award BIOS "Chipset Registers"
* v1.16 05/19/2004-VT8623-8235-CLE26I01C-00
*/
/*
* First the northbridge.
*/
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_8623), 0);
/*
* PCI Buffer control
*
* Enable CPU to PCI Post-Write
* PCI Master to DRAM Always Prefetch
* Disable PCI Master Read Caching
* Enable delay transaction
*/
SET_CHIPSET_REG(dev, 0x70, 0xB6, 0x82);
/*
* CPU to PCI Flow Control
*
* Flush buffer or return FFFFFFFFh for reads.
* Retry 2 times, backoff CPU
* Enable PCI Burst
* Disable type #1 configuration cycles
* IDSEL control: AD11, AD12
*/
SET_CHIPSET_REG(dev, 0x71, 0x7B, 0x48);
/*
* PCI Master Control
*
* PCI Master zero-wait-state write trdy# response
* PCI Master zero-wait-state read trdy# response
* Disable WSC#
* Enable PCI Master Broken Timer
*/
SET_CHIPSET_REG(dev, 0x73, 0x71, 0x01);
/*
* PCI Arbitration 1
*
* Arbitration mode: REQ based
* PCI Master bus Time-Out 1x16 PCICLKs
*/
SET_CHIPSET_REG(dev, 0x75, 0xFF, 0x01);
/*
* PCI Arbitration 2
*
* Grant Master Priority Rotation Control to CPU after every PCI master
* grant
*/
SET_CHIPSET_REG(dev, 0x76, 0x3D, 0x10);
/*
* AGP Control
*
* Disable AGP read syncronization
* Enable AGP Read Snoop DRAM Post-Write buffer
* Enable Fence/Flush
* AGP Grant Parking
* AGP to PCI Master / CPU to PCI turnaround cycle 1T timing
*/
SET_CHIPSET_REG(dev, 0xAC, 0x67, 0x2F);
SET_CHIPSET_REG(dev, 0x76, 0x3D, 0x10);
/*
* Unknown.
*/
SET_CHIPSET_REG(dev, 0xB0, 0xC0, 0x00);
SET_CHIPSET_REG(dev, 0xB1, 0xFF, 0xDA);
SET_CHIPSET_REG(dev, 0xB2, 0x10, 0x10);
/*
* Then the AGP bridge
*/
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_8633_1), 0);
SET_CHIPSET_REG(dev, 0x40, 0xBF, 0x83);
SET_CHIPSET_REG(dev, 0x41, 0xFF, 0x45);
SET_CHIPSET_REG(dev, 0x43, 0xFF, 0x44);
SET_CHIPSET_REG(dev, 0x44, 0xBF, 0x34);
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_8235), 0);
if (dev == PCI_DEV_INVALID) {
die("Southbridge not found!!!\n");
}
SET_CHIPSET_REG(dev, 0x40, 0x61, 0x41);
SET_CHIPSET_REG(dev, 0x42, 0xF0, 0xF0);
SET_CHIPSET_REG(dev, 0x4C, 0xC0, 0x40);
SET_CHIPSET_REG(dev, 0x58, 0xFF, 0x01);
SET_CHIPSET_REG(dev, 0x81, 0x04, 0x04);
SET_CHIPSET_REG(dev, 0x8D, 0xF0, 0x90);
SET_CHIPSET_REG(dev, 0x8D, 0xF0, 0x10);
print_debug("Dumping southbridge:\n");
for (r = 0; r < 256; r += 16) {
print_debug_hex8(r);
print_debug(": ");
for(c = 0; c < 16; c++) {
print_debug_hex8(pci_read_config8(dev, r+c));
print_debug(" ");
}
print_debug("\r\n");
}
pci_write_config8(dev, 0x50, 0);
pci_write_config8(dev, 0x51, 0x1d);
pci_write_config8(dev, 0x94, 0xa0);
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_82C586_1), 0);
pci_write_config8(dev, 0x42, 0);
SET_CHIPSET_REG(dev, 0x04, 0xFF, 0x07);
SET_CHIPSET_REG(dev, 0x05, 0xFF, 0x00);
SET_CHIPSET_REG(dev, 0x43, 0x0F, 0x05);
SET_CHIPSET_REG(dev, 0x45, 0x0C, 0x0C);
}
static void enable_shadow_ram(void)
{
device_t dev = 0; /* no need to look up 0:0.0 */
unsigned char shadowreg;
/* dev 0 for southbridge */
shadowreg = pci_read_config8(dev, 0x63);
/* 0xf0000-0xfffff */
shadowreg |= 0x30;
pci_write_config8(dev, 0x63, shadowreg);
}
static void main(unsigned long bist)
{
unsigned long x;
device_t dev;
if (bist == 0) {
early_mtrr_init();
}
enable_vt8235_serial();
uart_init();
console_init();
print_info("In auto.c:main()\n");
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
/* init_timer();*/
outb(5, 0x80);
print_info(" Doing odd PCI config\n");
pci_write_config8( 0xd*8,0x15,0x1c);
pci_write_config8( 0 , 0xe1, 0xdd);
outb(5, 0x80);
print_info(" Enabling mainboard devices\n");
enable_mainboard_devices();
print_info(" Enabling smbus\n");
enable_smbus();
print_info(" Enabling shadow ram\n");
enable_shadow_ram();
/*
memreset_setup();
this is way more generic than we need.
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
*/
sdram_set_registers((const struct mem_controller *) 0);
sdram_set_spd_registers((const struct mem_controller *) 0);
sdram_enable(0, (const struct mem_controller *) 0);
/* Check all of memory */
#if 0
ram_check(0x00000000, msr.lo);
#endif
#if 0
static const struct {
unsigned long lo, hi;
} check_addrs[] = {
/* Check 16MB of memory @ 0*/
{ 0x00000000, 0x01000000 },
#if TOTAL_CPUS > 1
/* Check 16MB of memory @ 2GB */
{ 0x80000000, 0x81000000 },
#endif
};
int i;
for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
ram_check(check_addrs[i].lo, check_addrs[i].hi);
}
#endif
print_info("Leaving auto.c:main()\n");
}
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