Bari Ari <[EMAIL PROTECTED]> wrote: > The TM5800 can directly address 4GB of memory space since it is a 32 bit > cpu. However the maximum memory size in the DIMM sockets the TM5800 can > address is 1025MB
1024 MB you mean? If only 1 GB can go in DIMM sockets, where can the remaining 3 GB go? > arranged as two banks of 512MB or four banks of 256MB. Is "bank" = "1 DIMM module" or? > Design of the memory controller silicon Is the memory controller silicon inside the TM5800, or is it some separate chip? > Look for modules that that minimize the number of loads. What are "loads"? > The SDRAM interface cannot drive more than sixteen unbuffered devices. > SDR SDRAM configurations requiring more than sixteen loads must use > buffered SDR memory. But I am talking about DDR here, not SDR. TM5800 does not support buffered memory: http://transmeta.com/crusoe_docs/TM5800v2.1_databook_030922.pdf Page 2, section 1.2.1 -- Miernik _________________________ xmpp:[EMAIL PROTECTED] ___________________/_______________________/ mailto:[EMAIL PROTECTED] Protect Europe from a legal disaster. Petition against software patents http://www.noepatents.org/index_html?LANG=en -- LinuxBIOS mailing list [email protected] http://www.openbios.org/mailman/listinfo/linuxbios
