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http://bbs.chinaunix.net/archiver/tid-1218105.html daschina SUN
SIRE V250 错误
此机器原来的内存全丢了，现在插了一根SAMSUNG的1G ECC的条,是不是内存方面的原因?位置不对吗? 只插了一根条子,另外一个CPU还运行吗? 终端输出如下: SC Alert: Host System has Reset 0>@(#) Sun Blade[TM] 2500 POST 4.11.4 2003/07/23 11:37 /export/common-source/firmware_re/post/post-build-4.11.4/Fiesta/enchilada /integrated (firmware_re) 0>Soft Power-on RST thru SW 0>CPUs present in system: 0 1 0>OBP->POST Call with %o0=00000000.050 0>Diag level set to MIN. 0>MFG scrpt mode set to NONE 0>I/O port set to TTYA. 0> 0>Start selftest... 0>Init SB 0>Init CPU 0>DMMU 0>DMMU TLB DATA RAM Access 0>DMMU TLB TAGS Access 0>IMMU Registers Access 0>IMMU TLB DATA RAM Access 0>IMMU TLB TAGS Access 0>Init mmu regs 0>Setup L2 Cache 0>L2 Cache Control = 00000000.00f04400 0> Size = 00000000.00100000... 0>Scrub and Setup L2 Cache 0>Setup and Enable DMMU 0>Setup DMMU Miss Handler 0>Test and Init Temp Mailbox 0>CPU Tick and Tick Compare Registers Test 0>CPU Stick and Stick Compare Registers Test SC Alert: Host system h 0>Set Timing 0> UltraSPARC[TM] IIIi, Version 2.4gin timeout, returns to console stream. 1>Init CPU 1> UltraSPARC[TM] IIIi, Version 2.4 to return to ALOM. 1>DMMU SC Al 1>DMMU TLB DATA RAM Accessown. 1>DMMU TLB TAGS Accessch set to diagnostic p 1>IMMU Registers Access @ 1>IMMU TLB DATA RAM Access:03 Sun Blade 2500,Sun Fir 1>IMMU TLB TAGS Access 1>Init mmu regs Clearing 1>Setup L2 Cache Power-On Reset 1>L2 Cache Control = 00000000.00f04400st 0>@ 1> Size = 00000000.00100000...003/07/23 11:37 1>Scrub and Setup L2 Cache /export/com 1>Setup and Enable DMMUost/post-build-4.11.4/F 1>Setup DMMU Miss Handler 1>Test and Init Temp Mailbox /integrated 1>CPU Tick and Tick Compar 0>MB: Part-Dash-Rev#: 3753130-02-50 Serial#: 013947rt selftest... 0>Init SB 0>I 0>Set CPU/System SpeedU 0>DMMU TLB DAT 0>MCR Timing index = 00000000.000000020>DMMU TLB TAGS Access 0>.. 0> 0>Send MC Timing CPU 1 0>Probe DimmsA RAM Access 1>Probe Dimms 0 1>MU 1>ERROR: TEST = Probe Dimms 0>Init mmu regs 1>H/W under test = CPU1: Bank2 DIMM6, MotherboardL2 Cache Control = 00000000.00f04400 1>Repair Instructions: Replace items in order listed by 'H/W under test' above 0>Scrub and Setup L2 Cache 0>Setup 1>MSG = Dimm Pair incomplete. 0>Soft Power-on RST thru SW 1>DMMU TLB TAG 0>CPUs present in system: 0 1 1>IMMU Registers Access 0> 0>Resume selftest...TLB DATA RAM Access 0>Init SB 0>Init CPUMU TLB TAG 0>Init mmu regs 0>Setup L2 Cache 1> 0>L2 Cache Control = 00000000.00f04400he Control = 00000000.00f04400 0> Size = 00000000.00100000... Size = 00000000.00100000... 0>Setup and Enable DMMU 1>Scrub and Setu 0>Setup DMMU Miss Handler 1> Size = 00000000.00100000... 0>Initialize I2C Control 1>Setup and Enable DMMU 0>MB: Part-Das 1>Setup DMMU Miss Handlerrial#: 013947 1>Timing is 8:1 10:1, sys 159 MHz, CPU 1279 MHz, mem 127 MHz. Speed 0>MCR Timing index = 00000000.00 0>Initialize I2C Controller 0>.. 0 1>Init Mem Controller Sequence 0>Probe Dimms 0>Init Mem Controller Sequence 1> 1>ERROR: TEST = Pro 0>IO-Bridge unit 0 init test 1>H/W under test = CP 0>IO-Bridge unit 1 init te 0>END_ERRORem frequenc 1>Soft Power-on RST thru SW MHz 1>CPUs present in system: 0 1 0>S 1>OBP->POST Call with %o0=00000000.05002000. 0>CPUs present in system: 0 1 1>Diag level set to MIN. 0>Resume selftest... 1>MFG scrpt mode set to NONE 0>Init CPU 1>I/O port set to TTYA. 0>Setup L2 Cac 1> 1>Start selftest... 1>IMMU TLB TAGS Access59 MHz, CPU 1279 MHz, 1>Init mmu regs 1>Setup L2 Cache 1>L2 Cache Control = 00000000.00f04400Version 2.4 1> Size = 00000000.00100000...> UltraSPARC[TM] IIIi, Version 1>Scrub and Setup L2 Cache 1>Init m 1>Setup and Enable DMMU>Setup L2 Cache 1>Setup DMMU Miss Handlerl = 00000000.00f04400 1>Test and Init Temp Mailbox 1> Size = 0000000 1>CPU Tick and Tick Compare Registers Test 1>Setup and Enable DMMU 1>CPU Stick and Stick Compare Registers Test 1>Timing is 8:1 10:1, sys 1 1>Set Timing279 MHz, mem 1> UltraSPARC[TM] IIIi, Version 2.4 0>Initiali 0>Init CPU 0> 0>IMMU TLB DATA RAM Access 0>Probe and Se 0>IMMU TLB TAGS Access 0>INFO: No 0>Init mmu regs 0>Setup L2 Cache0>ERROR: TEST = 0>L2 Cache Control = 00000000.00f04400 0>H/W under test 0> Size = 00000000.00100000... 0>Repair Instructions: Rep 0>Scrub and Setup L2 Cacheby 'H/W under test' above 0>Setup and Enable DMMU 0>Setup DMMU Miss Handler 0>MSG = No good memo 0>Test and Init Temp Mailbox rolling over to new Master. 0>CPU Tick and Tick Compare Registers Test 0>END_E 0>CPU Stick and Stick Compare Registers Test 1>CPUs present in 0>Setup Int Handlers 1>Setup Int Handlersh %o0= 1>Send MC Timing CPU 0LB DATA RAM Access 1>Probe Dimms 1>IM 1>TL 1>ERROR: TEST = Probe Dimms 1>Init mmu regs 1>H/W under test = CPU1: Bank2 DIMM6, MotherboardCache Control = 00000000.00f04400 1>Repair Instructions: Replace items in order listed by 'H/W under test' above 1>Scrub and Setup L2 Cache 1>Setup an 1>MSG = Dimm Pair incomplete. 1>Setup DMMU Miss Hand 1>END_ERROR 0>Probe Dimmsd Init Temp M 0>Init Mem Controller Regs 1>CPU Tick and Tic 1>Init Mem Controller Regs 0>Set JBUS config re 0 1>MU 1>Resume selftest... 1>Init SBMU TLB TA 1>Init CPU 1>Init mmu regst mmu regs 1>Setup L2 Cachep L2 Cache 1>L2 Cache Control = 00000000.00f044000.00f04400 1> Size = 00000000.00100000...0100000... 1>Setup and Enable DMMUetup L2 Cache 1>Setup DMMU Miss Handlernd Enable DMMU 1>Timing is 8:1 10:1, sys 159 MHz, CPU 1279 MHz, mem 127 MHz. 0>Test and Init Temp Mailbox 0> 1> UltraSPARC[TM] I 0>L2 Cache Control = 00000000.00f044000>Send Int to Master CPU 0> Size = 00000000.00100000...er 1>MB: 0>Setup and Enable DMMU130-02-50 Serial#: 01 0>Setup DMMU Miss Handler 0>Timing is 8:1 10:1, sys 159 MHz, CPU 1279 MHz, mem 127 MHz.iming index = 00000000.00000002 1>Initialize I2C ControllerTiming CPU 0 0>Init Mem Controller Sequence 1> 1>ERROR: TEST = Probe 1>Init Mem Controller Sequence 1>H/W under test = CPU1: Ba 1>IO-Bridge unit 0 init test 1>IO-Bridge unit 1 init testuctions: Replace items in or 1>Select Bank Configder test' above 1>MSG = No good memory available on master CPU 1, rolling over to new Master. 1>END_ERROR 1>ERROR: 1> POST toplevel status has the following failures: 1> CPU1: Bank2 DIMM6, Motherboard 1>END_ERROR 1> 1>ERROR: No good CPUs OR CPUs with good memory left. Calling debug menu. 1> 0 Peek/Poke interface 1> 1 Dump CPU Regs 1> 2 Dump Mem Controller Regs 1> 3 Dump Valid DMMU entries 1> 4 Dump IMMU entries 1> 5 Dump Mailbox 1> 6 Dump IO-Bridge regs unit 0 1> 7 Dump IO-Bridge regs unit 1 1> 8 Allow other CPUs to print 1> 9 Do soft reset 1> ? Help 1> 1>Selection: |
