[linuxkernelnewbies] WoSPS: Workshop on Soft Processor Systems

[Peter Teoh]

http://www.eecg.toronto.edu/wosps08/ WoSPS: Workshop on Soft Processor Systems In conjunction with the The Seventeenth International Conference on Parallel Architectures and Compilation Techniques (PACT) Sunday/26 of October 2008 (1:30pm) Toronto, Ontario, Canada Overview: Processors implemented in programmable logic, called soft processors, are becoming increasingly important in both industry and academia. FPGA-based processors provide an easy way for software programmers to target FPGAs without having to write hardware-description language---hence designers of FPGA-based embedded systems are increasingly including soft processors in their designs. Soft processors will also likely play an important role in FPGA-based co-processors for high-performance computing. Furthermore, academics are embracing FPGA-based processors as the foundation of systems for faster architectural simulation. In all cases, we need to develop a deeper understanding of processor and multiprocessor architecture for this new medium. This workshop will serve as a forum for academia and industry to discuss and present challenges, ideas, and recent developments in soft processors, soft multiprocessors, application-specific soft processors, and soft-processor-based accelerators and architectural simulation platforms. Call for Papers Important Dates Submission: Friday September 5, 2008 deadline extended to Monday September 8, 2008 Author notification: Monday September 22, 2008 PACT early registration deadline: Thurdsay September 25, 2008 Final version: Monday October 6, 2008 Registration Please register for the workshop through the main PACT registration page Final Program Session 1: 1:30-3:00pm Programming Soft Processors in High Performance Reconfigurable Computing (pdf), Andrew W. H. House and Paul Chow, U of Toronto Relocation of FPGA Partial Configuration Bit-Streams for Soft-Core Microprocessors (pdf), Jeff Carver, Neil Pittman, Alessandro Forin, Microsoft Research Automatic Generation of Interrupt-Aware Hardware Accelerators with the M2V Compiler (pdf), Abilash Sekar* and Alessandro Forin**, *Georgia Institute of Technology, **Microsoft Research Session 2: 3:20-5:00pm Improving Memory System Performance for Soft Vector Processors (pdf), Peter Yiannacouras, J. Gregory Steffan, and Jonathan Rose, U of Toronto On Transparently Exploiting Data-level Parallelism on Soft-processors (pdf), Bojan Mihajlovic, Zeljko Zilic, and Warren Gross, McGill (short talk) Challenges in Compilation of Brook Streaming Programs for FPGAs (pdf), Franjo Plavec, Zvonko Vranesic, and Stephen Brown, U of Toronto (short talk) A GPU-Like Soft Processor for High Throughput Acceleration (pdf), Jeffrey Kingyens and J. Gregory Steffan, U of Toronto (short talk) Committee Kubilay Atasu, IBM Steve Brown, Toronto/Altera Guy Lemieux, UBC Wayne Luk, Imperial College Naraig Manjikian, Queens Mazen Saghir, AUB Greg Steffan, Toronto (Organizer)