[linuxkernelnewbies] Direct Memory Access (DMA) and Interrupt Handling

Sun, 26 Apr 2009 18:45:55 -0700

http://www.eventhelix.com/RealtimeMantra/FaultHandling/dma_interrupt_handling.htm

DMA and Interrupt Handling

In this series on hardware basics, we have already looked at read and write bus cycles. In this article we will cover Direct Memory Access (DMA) and Interrupt Handling. Knowledge of DMA and interrupt handling would be useful in writing code that interfaces directly with IO devices (DMA based serial port design pattern is a good example of such a device).

We will discuss the following topics:

Direct Memory Access (DMA) A typical DMA operation is described here. Interactions between the main CPU and DMA device are covered. The impact of DMA on processor's internal cache is also covered.
Interrupt Handling Processor handling of hardware interrupts is described in this section. 
Interrupt Acknowledge Cycle Many processors allow the interrupting hardware device to identify itself. This speeds up interrupt handling as the processor can directly invoke the interrupt service routine for the right device.
Synchronization Requirements for DMA and Interrupts Software designers need to keep in mind that DMA operations can be triggered at bus cycle boundary while interrupts can only be triggered at instruction boundary.

Direct Memory Access (DMA)

  1. Device wishing to perform DMA asserts the processors bus request signal.
  2. Processor completes the current bus cycle and then asserts the bus grant signal to the device.
  3. The device then asserts the bus grant ack signal.
  4. The processor senses in the change in the state of bus grant ack signal and starts listening to the data and address bus for DMA activity.
  5. The DMA device performs the transfer from the source to destination address.
  6. During these transfers, the processor monitors the addresses on the bus and checks if any location modified during DMA operations is cached in the processor. If the processor detects a cached address on the bus, it can take one of the two actions:
    • Processor invalidates the internal cache entry for the address involved in DMA write operation
    • Processor updates the internal cache when a DMA write is detected
  7. Once the DMA operations have been completed, the device releases the bus by asserting the bus release signal.
  8. Processor acknowledges the bus release and resumes its bus cycles from the point it left off.

Interrupt Handling

Here we describe interrupt handling in a scenario where the hardware does not support identifying the device that initiated the interrupt. In such cases, the possible interrupting devices need to be polled in software.

  1. A device asserts the interrupt signal at a hardwired interrupt level.
  2. The processor registers the interrupt and waits to finish the current instruction execution.
  3. Once the current instruction execution is completed, the processor initiates the interrupt handling by saving the current register contents on the stack.
  4. The processor then switches to supervisor mode and initiates an interrupt acknowledge cycle.
  5. No device responds to the interrupt acknowledge cycle, so the processor fetches the vector corresponding to the interrupt level.
  6. The address found at the vector is the address of the interrupt service routine (ISR).
  7. The ISR polls all the devices to find the device that caused the interrupt. This is accomplished by checking the interrupt status registers on the devices that could have triggered the interrupt.
  8. Once the device is located, control is transferred to the handler specific to the interrupting device.
  9. After the device specific ISR routine has performed its job, the ISR executes the "return from interrupt" instruction.
  10. Execution of the "return from interrupt" instruction results in restoring the processor state. The processor is restored back to user mode.

Interrupt Acknowledge Cycle

Here we describe interrupt handling in a scenario where the hardware does support identifying the device that initiated the interrupt. In such cases, the exact source of the interrupt can be identified at hardware level.

  1. A device asserts the interrupt signal at a hardwired interrupt level.
  2. The processor registers the interrupt and waits to finish the current instruction execution.
  3. Once the current instruction execution is completed, the processor initiates the interrupt handling by saving the current register contents on the stack.
  4. The processor then switches to supervisor mode and initiates an interrupt acknowledge cycle.
  5. The interrupting device responds to the interrupt acknowledge cycle with the vector number for the interrupt.
  6. Processor uses the vector number obtained above and fetches the vector.
  7. The address found at the vector is the address of the interrupt service routine (ISR) for the interrupting device.
  8. After the  ISR routine has performed its job, the ISR executes the "return from interrupt" instruction.
  9. Execution of the "return from interrupt" instruction results in restoring the processor state. The processor is restored back to user mode.

Synchronization Requirements for DMA and Interrupts

Many times software designers have to work with data structures that are shared with interrupts or DMA devices. This requires performing atomic updates to the shared critical regions.

Synchronization With Interrupts

When a data structure is shared with an ISR, disabling the interrupt to execute the critical region updates is a good technique. Keep in mind that disabling of interrupts should be restricted to only the code that updates the critical region. Keeping the interrupts disabled for a long time will increase the interrupt latency. 

Another option is to make use of the fact that interrupts are processed at instruction boundaries. A single instruction that performs read as well as write could be used to perform an atomic transaction. For example, if your processor supports direct memory increment, you could increment a shared semaphore without disabling interrupts.

 Synchronization With DMA

Sharing data structures with a DMA device is tricky. The processor can initiate a DMA operation at a bus cycle boundary. This means that a new DMA operation can be started in the middle of an instruction execution (Keep in mind that an instruction execution involves multiple bus cycles).

The best mechanism to perform critical region updates is to use the read-modify-write bus cycle. With this instruction, atomic updates can be made to critical regions as the read and write are glued together in a special bus cycle. 

Another option is to disable DMA operation. Extreme caution should be used when employing these techniques.

  • Some processors also support disabling DMA operations by using locked bus cycles. The processor could execute lock instruction to disable external bus grants. When critical region updates have been completed, the unlock instruction is used to allow bus grants.
  • Another mechanism to prevent DMA might be to temporarily disable the device that will perform DMA. For example, if the DMA operations are being performed by an Ethernet controller, disabling the Ethernet controller will make sure no DMA operations are started when a critical region update is being made.

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