[linuxkernelnewbies] Eureka Technology - CPU interface cores for PowerPC, ARM, MIPS processors for SoC design

[Peter Teoh]

http://www.eurekatech.com/products/cpu.htm Eureka Technology, Inc. provides interface cores to all the popular CPUs for SoC design. AHB Bus Slave AHB Bus Master AHB to SDRAM Controller AHB to DDR SDRAM Controller AHB to PCI Host Bridge AHB DMA Controller PowerPC Bus Master PowerPC Bus Slave PowerPC to PCI Host Bridge PowerPC Bus Arbiter SysAD Bus Slave SysAD Bus to PCI Host Bridge EC Interface Bus Slave EC Interface to SDRAM Controller EC Interface to PCI Host Bridge   AHB Bus Slave AHB bus slave is designed to interface between multiple user-defined logics to the ARM CPU on the AMBA AHB bus. Concurrent data transfer between multiple user logics. Delay read transaction prevents system deadlock. All AHB bus transfer size and data width are supported. Optimized for ASIC and FPGA implementation including Excalibur PLD.   AHB Bus Master Initiate data transaction on the AHB bus master. Allowed user-defined logic such as DMA or peripheral bus controllers to access system resources on the AMBA AHB bus. Compatible with AHB bus protocol. Supports all AHB bus slave response types. Burst and single data transfers, including zero wait state data bursting. Bus arbitration and automatic transfer retry.   AHB to SDRAM Controller This controller provides high speed SDRAM data access to the ARM CPU and user-defined logic. Two port architecture provides sharing of memory without consuming data bandwidth on the AMBA AHB bus. Provides direct access from AHB bus to standard SDRAM devices. Shared memory between AHB bus and user-defined logics. Programmable SDRAM architecture and timing parameters. Fast page access on page hit. Pipeline access by user port to maximize bandwidth.   AHB to DDR SDRAM Controller This controller provides high speed DDR SDRAM data access to the ARM CPU and user-defined logic. Two port architecture provides sharing of memory without consuming data bandwidth on the AMBA AHB bus. Operates on both discrete DDR SDRAM chips and DDR SDRAM DIMM. External pin reduction by transferring two bits of data per pin. Programmable memory size and timing parameters.   AHB to PCI Host Bridge This controller allows the ARM CPU to initialize and access all PCI devices. It also provides external PCI devices access path to system resources on the AMB AHB bus. Compliant with PCI spec 2.2. Upstream and downstream data transfer. AHB bus and PCI bus runs at different clock domains. Multiple data buffer to speed up data transfer and prevents deadlock.   AHB DMA Controller This DMA controller is designed to operate directly on the AMBA AHB bus. It supports multiple independent channels and scatter-gather. Supports burst transfer to maximize data bandwidth. Supports both hardware and software initiated transfers. Scatter-gather allows DMA to merge multiple data source to contiguous space. Interrupt generation on transfer completion. PowerPC Bus Master This PowerPC bus interface core is designed to initiate read/write data transfer on the PowerPC CPU host bus. Typically the master is connected to a DMA controller or a bus snooping device on the user back-end. Compatible for PowerPC 601, 603, 604, 740, 750 and MPC860 microprocessors. Supports address pipeline, address retry, zero-wait state transfer, bus parking and snooping.   PowerPC Bus Slave This PowerPC bus interface core is designed as a target for CPU or other bus master access. It can be used as an interface between the CPU or between the CPU and the system core logic or between the CPU and the memory subsystem. Many system level functions such as control registers can be incorporated into the PowerPC slave. Supports all the functions of a PowerPC CPU and PowerPC bus master. Supports address pipeline, address retry, zero-wait state transfer. Direct interface to SRAM, BSRAM, FLASH and other memory devices.   PowerPC to PCI Host Bridge This PowerPC IP core allows the CPU to access the PCI bus recources and to configure the PCI bus under software control. Many design options are possible on the host bridge. Synchronous or Asynchronous clock between PowerPC and PCI bus. 64 and 32 bit support. Big endian and small endian conversion between the two buses.   PowerPC Bus Arbiter This PowerPC bus interface core arbitrates between multiple bus masters on the PowerPC bus. It arbitrates both the address tenure and the data bus tenure of the PowerPC host bus. Address only cycle and special snoop only devices are supported. Rotating priority, fixed priority, and bus parking are also implemented.   MIPS SysAD Bus Slave This module interfaces between the MIPS CPU on SysAD bus to system and I/O resources. Requests received from the processor are dispatched to different destinations based on programmable address mapping. SDRAM, FLASH, Serial I/O, PCI host bridge are supported. Concurrent read and write from different destinations. Out-or-order read data return. CPU boot vector initialization.   MIPS SysAD Bus to PCI Host Bridge This controller allows the MIPS CPU to initialize and access all PCI devices. It also provides external PCI devices access path to system resources on user-defined modules. Compliant with PCI spec 2.2. Upstream and downstream data transfer. SysAD bus and PCI bus runs at different clock domains. Multiple data buffer to speed up data transfer.   MIPS EC Interface Bus Slave This module interfaces between the MIPS CPU on EC interface to system and I/O resources. It supports the MIPS64 5K and MIPS32 4K processor core families. Multiple user interface ports. Concurrent read and write from different destinations. Address pipeline. Separate read and write data phase with out-of-order access completion.   MIPS EC Interface to SDRAM Controller This controller provides high speed SDRAM data access to the MIPS CPU and user-defined logic. Two port architecture provides sharing of memory without consuming data bandwidth on the EC bus. Provides direct access from EC bus to standard SDRAM devices. Shared memory between EC bus and user-defined logics. Programmable SDRAM architecture and timing parameters. Fast page access on page hit. Pipeline access by user port to maximize bandwidth.   MIPS EC interface to PCI Host Bridge This controller allows the MIPS CPU core to initialize and access all PCI devices. It also provides external PCI devices access path to system resources on user-defined modules. Compliant with PCI spec 2.2. Upstream and downstream data transfer. EC interface and PCI bus runs at different clock domains. Multiple data buffer to speed up data transfer.