[linuxkernelnewbies] MWAIT--Monitor Wait

[peter teoh]

http://www.intel.com/software/products/documentation/vlin/mergedprojects/analyzer_ec/mergedProjects/reference_olh/mergedProjects/instructions/instruct32_hh/MWAIT--Monitor_Wait.htm MWAIT--Monitor Wait Instruction Description MWAIT EAX, ECX A hint that allows the processor to stop instruction execution and enter an implementation-dependent optimized state until occurrence of a class of events.   Description The MWAIT instruction is designed to operate with the MONITOR instruction to allow a processor to signal an address on which to wait (MONITOR) and an instruction that causes the wait operation to commence (MWAIT). The MWAIT instruction is also a hint to the processor that it can choose to enter an implementation-dependent state while waiting for an event or for the store to the address range set up by the preceding MONITOR instruction in program flow. A given implementation may choose to ignore the hint and continue executing the next instruction. Future processor implementations may implement several optimized wait states and will select among those states based on the hint argument. In future processor designs, EAX and ECX will be used to communicate other information to the MWAIT instruction, such as the kind of optimized state the processor should enter. ECX specifies optional extensions for the MWAIT instruction. EAX may contain hints such as the preferred optimized state the processor should enter. For Intel(R) Pentium(R) 4 processors with SSE3, all non-zero values for EAX and ECX are reserved. The processor will raise a general protection fault on the execution of the MWAIT instruction with reserved values in ECX. The processor ignores setting of reserved bits in EDX. A store to the address range set by the MONITOR instruction, an interrupt, NMI, SMI, a debug exception, a machine check exception, the BINIT# signal, the INIT# signal, or the RESET# signal will exit the optimized state. Note that an interrupt will cause the processor to exit the optimized state only if the state was entered with interrupts enabled. If a store to the address range caused the processor to exit then execution will resume at the instruction following the MWAIT instruction. If an interrupt (including NMI) caused the processor to exit the optimized state, the processor will exit the optimized state and handle the interrupt. If an SMI caused the processor to exit the optimized state, execution will resume at the instruction following the MWAIT after handling of the SMI. Unlike the HALT instruction, the MWAIT instruction does not support a restart at the MWAIT instruction. There may also be other implementation-dependent events or time-outs that may take the processor out of the optimized state and resume execution at the instruction following the MWAIT. If the preceding MONITOR instruction did not successfully set an address range or if the MONITOR instruction has not been executed prior to executing MWAIT, then the processor will not enter the optimized state. Execution will resume at the instruction following the MWAIT. The MWAIT instruction can be executed at any privilege level. The MONITOR CPUID feature flag (bit 3 of ECX when CPUID is executed with EAX=1) indicates that a processor supports this instruction. The operating system or system BIOS may disable this instruction through the IA32_MISC_ENABLES MSR; disabling the instruction clears the CPUID feature flag and causes execution of the MWAIT instruction to generate an illegal opcode exception Operation // MWAIT takes the argument inEAX as a hint extension and is // architected to take the argument in ECX as an instruction extension // MWAIT EAX, ECX { WHILE (! ("monitor_event_pending_flag" OR "monitor_not_active")) { implementation_dependent_optimized_state(EAX, ECX); } Example The MONITOR and MWAIT instructions must be coded in the same loop because execution of the MWAIT instruction will clear the monitor address range. It is not possible to execute MONITOR once and then execute MWAIT in a loop. Setting up MONITOR without executing MWAIT has no adverse effects. Assume that there is a globally shared volatile integer trigger, that is written to zero (0x0) before the processor enters MWAIT, and written to one (0x1) by the other thread/processor that wants to wake this one up. Trigger = 0; If ( !trigger) { EAX = &trigger ECX = 0 EDX = 0 MONITOR EAX, ECX, EDX If ( !trigger ) { EAX = 0 ECX = 0 MWAIT EAX, ECX } } The above code sequence makes sure that a triggering store does not happen between the first check of the trigger and the execution of the monitor instruction. Without the second check that triggering store would go un-noticed. Typical usage of MONITOR and MWAIT would have the above code sequence within a loop. Exceptions None Numeric Exceptions None Protected Mode Exceptions #GP(0)For ECX has a value other than 0. #UDIf CPUID feature flag MONITOR is 0. If LOCK prefix is used. Real Address Mode Exceptions #GP(0)For ECX has a value other than 0. #UD If CPUID feature flag MONITOR is 0. If LOCK prefix is used. Virtual 8086 Mode Exceptions #GP(0) For ECX has a value other than 0. #UD If CPUID feature flag MONITOR is 0. If LOCK prefix is used.