25 Oct 2010...theARMarchitecture (available with theCortex-A15processor). LPAE comes with a
3-level page table format (compared to 2-level for the... lkml.org/lkml/2010/10/25/60-Cached
6 Dec 2010...On Thu, Dec 02, 2010 at
06:01:50PM +0000, Russell King -ARMLinux...Cortex-A15doesn't have a MMIO addressable
SCU at all.... https://lkml.org/lkml/2010/12/6/30-Cached
15 Nov 2010...theARMarchitecture (available with theCortex-A15processor). LPAE comes with a
3-level page table format (compared to 2-level for the... https://lkml.org/lkml/2010/11/15/301-Cached
4 Dec 2010...On Thu, Dec 02, 2010 at
06:01:50PM +0000, Russell King -ARMLinux wrote:...Cortex-A15doesn't have a MMIO addressable
SCU at all.... lkml.org/lkml/2010/12/4/12-Cached
2 Dec 2010...On 1 December 2010 00:25,
Russell King -ARMLinux...For example, the SCU onCortex-A15doesn't expose the core count... lkml.org/lkml/2010/12/2/175-Cached
2 Dec 2010...On 30 November 2010 22:16,
Russell King -ARMLinux...FYI,Cortex-A15comes with some
architected timers different from the... https://lkml.org/lkml/2010/12/2/159-Cached
25 Oct 2010...Subject, Re: [RFC PATCH 06/18]ARM: LPAE:
Introduce the 3-level...Cortex-A15comes with both LPAE and
Virtualisation Extensions, so the... lkml.org/lkml/2010/10/25/251-Cached
12 Nov 2010...theARMarchitecture (available with theCortex-A15processor). LPAE comes with a
3-level page table format (compared to 2-level for the... lkml.org/lkml/2010/11/12/296-Cached
14 Oct 2010...On aCortex-A8 if you
enable auxcr.asa speculative accesses will be allowed to happen more...I'm toldA15gets much more aggressive here.... lkml.org/lkml/2010/10/14/180-Cached