The QUICC Engine provides interrupts for a few I/O ports. This is
handled via a separate interrupt ID and managed via a triplet of
dedicated registers hosted by the SoC.
Implement an interrupt driver for it for that those IRQs can then
be linked to the related GPIOs.
Signed-off-by: Christophe Leroy <christophe.le...@csgroup.eu>
---
.../soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml | 63 +++++++++++++++++++
1 file changed, 63 insertions(+)
create mode 100644
Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml
diff --git
a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml
b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml
new file mode 100644
index 0000000000000..7c98706d03dd1
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+title: Freescale QUICC Engine I/O Ports Interrupt Controller
+
+maintainers:
+ - name: Christophe Leroy
+ email: christophe.le...@csgroup.eu
+
+description: |
+ Interrupt controller for the QUICC Engine I/O ports found on some
+ Freescale/NXP PowerQUICC and QorIQ SoCs.
+
+properties:
+ compatible:
+ enum:
+ - fsl,mpc8323-qe-ports-ic
+ - fsl,mpc8360-qe-ports-ic
+ - fsl,mpc8568-qe-ports-ic
+
+ reg:
+ description: Base address and size of the QE I/O Ports Interrupt
Controller registers.
+ minItems: 1
+ maxItems: 1
+
+ interrupt-controller:
+ type: boolean
+ description: Indicates this node is an interrupt controller.
+
+ '#address-cells':
+ const: 0
+ description: Must be 0.
+
+ '#interrupt-cells':
+ const: 1
+ description: Number of cells to encode an interrupt specifier.
+
+ interrupts:
+ minItems: 1
+ maxItems: 1
+ description: Interrupt line to which the QE I/O Ports controller is
connected.
+
+ interrupt-parent:
+ description: Phandle to the parent interrupt controller.
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - '#address-cells'
+ - '#interrupt-cells'
+ - interrupts
+ - interrupt-parent
+
+examples:
+ - |
+ interrupt-controller@c00 {
+ interrupt-controller;
+ compatible = "fsl,mpc8323-qe-ports-ic";
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0xc00 0x18>;
+ interrupts = <74 0x8>;
+ interrupt-parent = <&ipic>;
--
2.49.0
