Gerhard Pircher writes: > Yeah, the northbridge hates the M bit! Thus the AmigaOne platform code
Wow. > masks out the CPU_FTR_NEED_COHERENT flag and disables the L2 cache > prefetch engines (I don't care about the performance loss). > I couldn't find any other code that sets the M bit, except for huge TLB > page support, but isn't that only for PPC64? No it's not just for ppc64. We had a patch that went in some time ago to ensure that the M bit was set on various 32-bit platforms because otherwise we got data corruption (due to a small cache in the northbridge not being kept coherent with the processor cache). Look for CPU_FTR_NEED_COHERENT in include/asm-powerpc/cputable.h and arch/powerpc/mm/*. Paul. _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
