On platforms doing non-coherent DMA (4xx, 8xx, ...), it's important that kmalloc minimum alignment is set to the cache line size, to avoid sharing cache lines between different objects.
Signed-off-by: Benjamin Herrenschmidt <[EMAIL PROTECTED]> --- include/asm-powerpc/page_32.h | 4 ++++ 1 file changed, 4 insertions(+) Index: linux-work/include/asm-powerpc/page_32.h =================================================================== --- linux-work.orig/include/asm-powerpc/page_32.h 2007-11-19 15:01:08.000000000 +1100 +++ linux-work/include/asm-powerpc/page_32.h 2007-11-19 15:01:17.000000000 +1100 @@ -6,6 +6,10 @@ #define PPC_MEMSTART 0 +#ifdef CONFIG_NOT_COHERENT_CACHE +#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES +#endif + #ifndef __ASSEMBLY__ /* * The basic type of a PTE - 64 bits for those CPUs with > 32 bit _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
