On Mon, 2016-03-07 at 09:33 +1100, Oliver O'Halloran wrote:
> In save_sprs() in process.c contains the following test:
>
> if (cpu_has_feature(cpu_has_feature(CPU_FTR_ALTIVEC)))
> t->vrsave = mfspr(SPRN_VRSAVE);
>
> CPU feature with the mask 0x1 is CPU_FTR_COHERENT_ICACHE so the test
> is equivilent to:
>
> if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
> cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
>
> On CPUs without support for both (i.e G5) this results in vrsave not
> being
> saved between context switches. The vector register save/restore code
> doesn't use VRSAVE to determine which registers to save/restore,
> but the value of VRSAVE is used to determine if altivec is being used
> in several code paths.
Nice one, should probably go to stable !
> Signed-off-by: Oliver O'Halloran <ooh...@gmail.com>
> ---
> arch/powerpc/kernel/process.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/kernel/process.c
> b/arch/powerpc/kernel/process.c
> index 8224852..5a4d4d1 100644
> --- a/arch/powerpc/kernel/process.c
> +++ b/arch/powerpc/kernel/process.c
> @@ -855,7 +855,7 @@ void restore_tm_state(struct pt_regs *regs)
> static inline void save_sprs(struct thread_struct *t)
> {
> #ifdef CONFIG_ALTIVEC
> - if (cpu_has_feature(cpu_has_feature(CPU_FTR_ALTIVEC)))
> + if (cpu_has_feature(CPU_FTR_ALTIVEC))
> t->vrsave = mfspr(SPRN_VRSAVE);
> #endif
> #ifdef CONFIG_PPC_BOOK3S_64
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