Hi Laurent,
On Fri, Jul 29, 2016 at 11:51:22AM +0200, Laurent Dufour wrote:
> static int set_user_msr(struct task_struct *task, unsigned long msr)
> {
> +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
> + if (!(task->thread.regs->msr & MSR_TM)) {
> + /* If TM is not available, discard TM bits changes */
> + msr &= ~(MSR_TM | MSR_TS_MASK);
> + }
> +#endif
I am not sure whether following is an issue:
Per PowerISA, any exception/interrupt will disable MSR[TM] bit
automatically and mark MSR_TS to be suspended when it is
transactional. It is possible that MSR[TM] = 0 and MSR[MSR_TS] != 0
(suspended).
Will set_user_msr() be able to escape from the above?
For example, one user space application encountered
page fault during transaction, its task->thread.regs->msr & MSR_TM == 0
and MSR[MSR_TS] == suspended. Then it is being traced and
set_user_msr() is invoked on it. I think it will be incorrect to
clear its MSR_TS_MASK bits.....
Please correct me if I am wrong.
Thanks,
- Simon
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