On Tue, 2017-04-04 at 04:56:05 UTC, Paul Mackerras wrote: > In the past, there was only one load-with-reservation instruction, > lwarx, and if a program attempted a lwarx on a misaligned address, it > would take an alignment interrupt and the kernel handler would emulate > it as though it was lwzx, which was not really correct, but benign > since it is loading the right amount of data, and the lwarx should be > paired with a stwcx. to the same address, which would also cause an > alignment interrupt which would result in a SIGBUS being delivered to > the process. > > We now have 5 different sizes of load-with-reservation instruction. > Of those, lharx and ldarx cause an immediate SIGBUS by luck since > their entries in aligninfo[] overlap instructions which were not > fixed up, but lqarx overlaps with lhz and will be emulated as such. > lbarx can never generate an alignment interrupt since it only > operates on 1 byte. > > To straighten this out and fix the lqarx case, this adds code to > detect the l[hwdq]arx instructions and return without fixing them > up, resulting in a SIGBUS being delivered to the process. > > Signed-off-by: Paul Mackerras <pau...@ozlabs.org>
Applied to powerpc fixes, thanks. https://git.kernel.org/powerpc/c/48fe9e9488743eec9b7c1addd3c93f cheers