On Mon, Apr 10, 2017 at 04:53:18PM +0200, Juergen Schindele wrote:
> Dear mailing list,
> i found out on our platform with freescale mpc8315 SOC that in
> linux kernel code the setup of IRQ0 which we use is not correct.
> One should be able to use falling EDGE interrupt capabilities like on
> IRQ1-IRQ7. These setups are fixed in "arch/powerpc/sysdev/ipic.c"
> The internal interrupt number of IRQ0 is not like IRQ1-IRQ7 in one block
> but on number 48. To verify details please consult MPC8315ERM.pdf
> developpers manual.
>
> To correct these "EDGE" capabilities of IRQ0 i suggest the following
> patch:
> please consider integrating it to your patches.
>
>
> Thank you for your attention
>
> --- arch/powerpc/sysdev/ipic.c (Revision correct)
> +++ arch/powerpc/sysdev/ipic.c (Arbeitskopie)
> @@ -316,6 +316,7 @@
> .prio_mask = 7,
> },
> [48] = {
> + .ack = IPIC_SEPNR,
> .mask = IPIC_SEMSR,
> .prio = IPIC_SMPRR_A,
> .force = IPIC_SEFCR,
Could you send this with a signoff and a commit message intended for
merging?
-Scott
