Le 27/06/2017 à 14:32, David Laight a écrit :
From: Frederic Barrat
Sent: 26 June 2017 19:09
P9 has support for PCI peer-to-peer, enabling a device to write in the
mmio space of another device directly, without interrupting the CPU.
This patch adds support for it on powernv, by adding a new API to be
called by drivers. The pnv_pci_set_p2p(...) call configures an
'initiator', i.e the device which will issue the mmio operation, and a
'target', i.e. the device on the receiving side.
...
Two questions:
1) How does the driver get the correct address to give to the 'initiator'
in order to perform an access to the 'target'?
That's left out of this patch intentionally. The assumption is that
there's some handshake happening between the 2 drivers. But that's an
area where we could work to make it easier in the future.
2) Surely the API call the driver makes should be architecture neutral,
returning an error on other architectures.
The point of the patch is just to enable it on p9. I've heard of a more
generic, on-going effort, at the PCI API level, which would be
cross-arch. But here we just want to allow it for p9 to allow some early
drivers to take advantage of it if they choose to.
Fred
At least some x86 cpus also support peer-to-peer writes,
I believe they can work between cpu chips.
PCIe bridges might support them (or be configurable to support them).
David
