Oliver O'Halloran <ooh...@gmail.com> writes:
> The workaround for the CELL timebase bug does not correctly mark cr0 as
> being clobbered. This can result in GCC making some poor^W completely
> broken optimisations.
Fruit 'n oats, how did we never notice that? Luck I guess. Or subtle
breakage that no one could pin down :E
I'll tag it for stable.
Your change log is not entirely fair, it's not GCC's fault, we changed
register state without telling it, so it's on us :) I'll reword it a
bit here.
cheers
> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
> index 7e50e47375d6..a3b6575c7842 100644
> --- a/arch/powerpc/include/asm/reg.h
> +++ b/arch/powerpc/include/asm/reg.h
> @@ -1303,7 +1303,7 @@ static inline void msr_check_and_clear(unsigned long
> bits)
> " .llong 0\n" \
> ".previous" \
> : "=r" (rval) \
> - : "i" (CPU_FTR_CELL_TB_BUG), "i" (SPRN_TBRL)); \
> + : "i" (CPU_FTR_CELL_TB_BUG), "i" (SPRN_TBRL) : "cr0"); \
> rval;})
> #else
> #define mftb() ({unsigned long rval; \
> --
> 2.9.4
