The patch

   ASoC: fsl_ssi: Set xFEN0 and xFEN1 together

has been applied to the asoc tree at 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

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>From 702d7965e402a8dcd88e964fd5bba6f5f159d625 Mon Sep 17 00:00:00 2001
From: Nicolin Chen <>
Date: Mon, 12 Feb 2018 14:03:18 -0800
Subject: [PATCH] ASoC: fsl_ssi: Set xFEN0 and xFEN1 together

It'd be safer to enable both FIFOs for TX or RX at the same time.

Signed-off-by: Nicolin Chen <>
Tested-by: Caleb Crome <>
Tested-by: Maciej S. Szmigiero <>
Reviewed-by: Maciej S. Szmigiero <>
Signed-off-by: Mark Brown <>
 sound/soc/fsl/fsl_ssi.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 156f5132feba..00dfdc77b567 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -591,6 +591,11 @@ static void fsl_ssi_setup_regvals(struct fsl_ssi *ssi)
        if (fsl_ssi_is_ac97(ssi))
                vals[RX].scr = vals[TX].scr = 0;
+       if (ssi->use_dual_fifo) {
+               vals[RX].srcr |= SSI_SRCR_RFEN1;
+               vals[TX].stcr |= SSI_STCR_TFEN1;
+       }
        if (ssi->use_dma) {
                vals[RX].sier |= SSI_SIER_RDMAE;
                vals[TX].sier |= SSI_SIER_TDMAE;
@@ -991,14 +996,9 @@ static int _fsl_ssi_set_dai_fmt(struct device *dev,
                     SSI_SFCSR_TFWM0(wm) | SSI_SFCSR_RFWM0(wm) |
                     SSI_SFCSR_TFWM1(wm) | SSI_SFCSR_RFWM1(wm));
-       if (ssi->use_dual_fifo) {
-               regmap_update_bits(regs, REG_SSI_SRCR,
-                                  SSI_SRCR_RFEN1, SSI_SRCR_RFEN1);
-               regmap_update_bits(regs, REG_SSI_STCR,
-                                  SSI_STCR_TFEN1, SSI_STCR_TFEN1);
+       if (ssi->use_dual_fifo)
                regmap_update_bits(regs, REG_SSI_SCR,
                                   SSI_SCR_TCH_EN, SSI_SCR_TCH_EN);
-       }

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