The existing flush uses the radix value for sets, and uses R=0
tlbiel instructions. This can't be quite right, but I'm not entirely
sure if this is the right way to fix it.

Signed-off-by: Nicholas Piggin <npig...@gmail.com>
---
 arch/powerpc/kvm/book3s_hv_builtin.c | 14 +++++---------
 1 file changed, 5 insertions(+), 9 deletions(-)

diff --git a/arch/powerpc/kvm/book3s_hv_builtin.c 
b/arch/powerpc/kvm/book3s_hv_builtin.c
index 0b9b8e188bfa..577769fbfae9 100644
--- a/arch/powerpc/kvm/book3s_hv_builtin.c
+++ b/arch/powerpc/kvm/book3s_hv_builtin.c
@@ -676,7 +676,7 @@ static void wait_for_sync(struct kvm_split_mode *sip, int 
phase)
 
 void kvmhv_p9_set_lpcr(struct kvm_split_mode *sip)
 {
-       unsigned long rb, set;
+       struct kvm *kvm = local_paca->kvm_hstate.kvm_vcpu->kvm;
 
        /* wait for every other thread to get to real mode */
        wait_for_sync(sip, PHASE_REALMODE);
@@ -689,14 +689,10 @@ void kvmhv_p9_set_lpcr(struct kvm_split_mode *sip)
        /* Invalidate the TLB on thread 0 */
        if (local_paca->kvm_hstate.tid == 0) {
                sip->do_set = 0;
-               asm volatile("ptesync" : : : "memory");
-               for (set = 0; set < POWER9_TLB_SETS_RADIX; ++set) {
-                       rb = TLBIEL_INVAL_SET_LPID +
-                               (set << TLBIEL_INVAL_SET_SHIFT);
-                       asm volatile(PPC_TLBIEL(%0, %1, 0, 0, 0) : :
-                                    "r" (rb), "r" (0));
-               }
-               asm volatile("ptesync" : : : "memory");
+               if (kvm_is_radix(kvm))
+                       radix__local_flush_tlb_lpid(kvm->arch.lpid);
+               else
+                       hash__local_flush_tlb_lpid(kvm->arch.lpid);
        }
 
        /* indicate that we have done so and wait for others */
-- 
2.17.0

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