On Thu, 12 Apr 2018 23:47:51 +1000
Michael Ellerman <m...@ellerman.id.au> wrote:
> The cpu_has_feature() mechanism has an optimisation where at build
> time we construct a mask of the CPU feature bits that will always be
> true for the given .config, based on the platform/bitness/etc. that we
> are building for.
> That is incompatible with DT CPU features, where the set of CPU
> features is dependent on feature flags that are given to us by
> The result is that some feature bits can not be *disabled* by DT CPU
> features. Or more accurately, they can be disabled but they will still
> appear in the ALWAYS mask, meaning cpu_has_feature() will always
> return true for them.
> In the past this hasn't really been a problem because on Book3S
> 64 (where we support DT CPU features), the set of ALWAYS bits has been
> very small. That was because we always built for POWER4 and later,
> meaning the set of common bits was small.
> The only bit that could be cleared by DT CPU features that was also in
> the ALWAYS mask was CPU_FTR_NODSISRALIGN, and that was only used in
> the alignment handler to create a fake DSISR. That code was itself
> deleted in 31bfdb036f12 ("powerpc: Use instruction emulation
> infrastructure to handle alignment faults") (Sep 2017).
> However the set of ALWAYS features changed with the recent commit
> db5ae1c155af ("powerpc/64s: Refine feature sets for little endian
> builds") which restricted the set of feature flags when building
> little endian to Power7 or later. That caused the ALWAYS mask to
> become much larger for little endian builds.
> The result is that the following feature bits can currently not
> be *disabled* by DT CPU features:
> CPU_FTR_REAL_LE, CPU_FTR_MMCRA, CPU_FTR_CTRL, CPU_FTR_SMT,
> CPU_FTR_PURR, CPU_FTR_SPURR, CPU_FTR_DSCR, CPU_FTR_PKEY,
> CPU_FTR_VMX_COPY, CPU_FTR_CFAR, CPU_FTR_HAS_PPR.
> To fix it we need to mask the set of ALWAYS features with the base set
> of DT CPU features, ie. the features that are always enabled by DT CPU
> features. That way there are no bits in the ALWAYS mask that are not
> also always set by DT CPU features.
> Fixes: db5ae1c155af ("powerpc/64s: Refine feature sets for little endian
> Signed-off-by: Michael Ellerman <m...@ellerman.id.au>
Looks good to me.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>