On Thu, May 17, 2018 at 10:10:21PM +1000, Michael Ellerman wrote: > Christophe Leroy <christophe.le...@c-s.fr> writes: > > arch/powerpc/Makefile activates -mmultiple on BE PPC32 configs > > in order to use multiple word instructions in functions entry/exit > > True, though that could be a lot simpler because the MULTIPLEWORD value > is only used for PPC32, which is always big endian. I'll send a patch > for that.
Do you mean in the kernel? Many 32-bit processors can do LE, and many do not implement multiple or string insns in LE mode. > > The patch does the same for the asm parts, for consistency > > > > On processors like the 8xx on which insn fetching is pretty slow, > > this speeds up registers save/restore > > OK. I've always heard that they should be avoided, but that's coming > from 64-bit land. > > I guess we've been enabling this for all 32-bit targets for ever so it > must be a reasonable option. On 603, load multiple (and string) are one cycle slower than doing all the loads separately, and store is essentially the same as separate stores. On 7xx and 7xxx both loads and stores are one cycle slower as multiple than as separate insns. load/store multiple are nice for saving/storing registers. Segher