These flags are shared between Linux/KVM implementing the hypervisor
calls for the XIVE native exploitation mode and the driver for the
sPAPR guests.
Signed-off-by: Cédric Le Goater <c...@kaod.org>
---
arch/powerpc/include/asm/xive.h | 23 +++++++++++++++++++++++
arch/powerpc/sysdev/xive/spapr.c | 28 ++++++++--------------------
2 files changed, 31 insertions(+), 20 deletions(-)
diff --git a/arch/powerpc/include/asm/xive.h b/arch/powerpc/include/asm/xive.h
index 3c704f5dd3ae..32f033bfbf42 100644
--- a/arch/powerpc/include/asm/xive.h
+++ b/arch/powerpc/include/asm/xive.h
@@ -93,6 +93,29 @@ extern void xive_flush_interrupt(void);
/* xmon hook */
extern void xmon_xive_do_dump(int cpu);
+/*
+ * Hcall flags shared by the sPAPR backend and KVM
+ */
+
+/* H_INT_GET_SOURCE_INFO */
+#define XIVE_SPAPR_SRC_H_INT_ESB PPC_BIT(60)
+#define XIVE_SPAPR_SRC_LSI PPC_BIT(61)
+#define XIVE_SPAPR_SRC_TRIGGER PPC_BIT(62)
+#define XIVE_SPAPR_SRC_STORE_EOI PPC_BIT(63)
+
+/* H_INT_SET_SOURCE_CONFIG */
+#define XIVE_SPAPR_SRC_SET_EISN PPC_BIT(62)
+#define XIVE_SPAPR_SRC_MASK PPC_BIT(63) /* unused */
+
+/* H_INT_SET_QUEUE_CONFIG */
+#define XIVE_SPAPR_EQ_ALWAYS_NOTIFY PPC_BIT(63)
+
+/* H_INT_SET_QUEUE_CONFIG */
+#define XIVE_SPAPR_EQ_DEBUG PPC_BIT(63)
+
+/* H_INT_ESB */
+#define XIVE_SPAPR_ESB_STORE PPC_BIT(63)
+
/* APIs used by KVM */
extern u32 xive_native_default_eq_shift(void);
extern u32 xive_native_alloc_vp_block(u32 max_vcpus);
diff --git a/arch/powerpc/sysdev/xive/spapr.c b/arch/powerpc/sysdev/xive/spapr.c
index 575db3b06a6b..730284f838c8 100644
--- a/arch/powerpc/sysdev/xive/spapr.c
+++ b/arch/powerpc/sysdev/xive/spapr.c
@@ -184,9 +184,6 @@ static long plpar_int_get_source_info(unsigned long flags,
return 0;
}
-#define XIVE_SRC_SET_EISN (1ull << (63 - 62))
-#define XIVE_SRC_MASK (1ull << (63 - 63)) /* unused */
-
static long plpar_int_set_source_config(unsigned long flags,
unsigned long lisn,
unsigned long target,
@@ -243,8 +240,6 @@ static long plpar_int_get_queue_info(unsigned long flags,
return 0;
}
-#define XIVE_EQ_ALWAYS_NOTIFY (1ull << (63 - 63))
-
static long plpar_int_set_queue_config(unsigned long flags,
unsigned long target,
unsigned long priority,
@@ -286,8 +281,6 @@ static long plpar_int_sync(unsigned long flags, unsigned
long lisn)
return 0;
}
-#define XIVE_ESB_FLAG_STORE (1ull << (63 - 63))
-
static long plpar_int_esb(unsigned long flags,
unsigned long lisn,
unsigned long offset,
@@ -321,7 +314,7 @@ static u64 xive_spapr_esb_rw(u32 lisn, u32 offset, u64
data, bool write)
unsigned long read_data;
long rc;
- rc = plpar_int_esb(write ? XIVE_ESB_FLAG_STORE : 0,
+ rc = plpar_int_esb(write ? XIVE_SPAPR_ESB_STORE : 0,
lisn, offset, data, &read_data);
if (rc)
return -1;
@@ -329,11 +322,6 @@ static u64 xive_spapr_esb_rw(u32 lisn, u32 offset, u64
data, bool write)
return write ? 0 : read_data;
}
-#define XIVE_SRC_H_INT_ESB (1ull << (63 - 60))
-#define XIVE_SRC_LSI (1ull << (63 - 61))
-#define XIVE_SRC_TRIGGER (1ull << (63 - 62))
-#define XIVE_SRC_STORE_EOI (1ull << (63 - 63))
-
static int xive_spapr_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)
{
long rc;
@@ -349,11 +337,11 @@ static int xive_spapr_populate_irq_data(u32 hw_irq,
struct xive_irq_data *data)
if (rc)
return -EINVAL;
- if (flags & XIVE_SRC_H_INT_ESB)
+ if (flags & XIVE_SPAPR_SRC_H_INT_ESB)
data->flags |= XIVE_IRQ_FLAG_H_INT_ESB;
- if (flags & XIVE_SRC_STORE_EOI)
+ if (flags & XIVE_SPAPR_SRC_STORE_EOI)
data->flags |= XIVE_IRQ_FLAG_STORE_EOI;
- if (flags & XIVE_SRC_LSI)
+ if (flags & XIVE_SPAPR_SRC_LSI)
data->flags |= XIVE_IRQ_FLAG_LSI;
data->eoi_page = eoi_page;
data->esb_shift = esb_shift;
@@ -374,7 +362,7 @@ static int xive_spapr_populate_irq_data(u32 hw_irq, struct
xive_irq_data *data)
data->hw_irq = hw_irq;
/* Full function page supports trigger */
- if (flags & XIVE_SRC_TRIGGER) {
+ if (flags & XIVE_SPAPR_SRC_TRIGGER) {
data->trig_mmio = data->eoi_mmio;
return 0;
}
@@ -391,8 +379,8 @@ static int xive_spapr_configure_irq(u32 hw_irq, u32 target,
u8 prio, u32 sw_irq)
{
long rc;
- rc = plpar_int_set_source_config(XIVE_SRC_SET_EISN, hw_irq, target,
- prio, sw_irq);
+ rc = plpar_int_set_source_config(XIVE_SPAPR_SRC_SET_EISN, hw_irq,
+ target, prio, sw_irq);
return rc == 0 ? 0 : -ENXIO;
}
@@ -432,7 +420,7 @@ static int xive_spapr_configure_queue(u32 target, struct
xive_q *q, u8 prio,
q->eoi_phys = esn_page;
/* Default is to always notify */
- flags = XIVE_EQ_ALWAYS_NOTIFY;
+ flags = XIVE_SPAPR_EQ_ALWAYS_NOTIFY;
/* Configure and enable the queue in HW */
rc = plpar_int_set_queue_config(flags, target, prio, qpage_phys, order);
--
2.20.1
