Nicholas Piggin <npig...@gmail.com> writes:
> The slbfee. instruction must have bit 24 of RB clear, failure to do
> so can result in false negatives that result in incorrect assertions.
>
> This is not obvious from the ISA v3.0B document, which only says:
>
> The hardware ignores the contents of RB 36:38 40:63 -- p.1032
>
> This patch fixes the bug and also clears all other bits from PPC bit
> 36-63, which is good practice when dealing with reserved or ignored
> bits.
>
Reviewed-by: Aneesh Kumar K.V <aneesh.ku...@linux.ibm.com>
> Fixes: e15a4fea4d ("powerpc/64s/hash: Add some SLB debugging tests")
> Reported-by: Aneesh Kumar K.V <aneesh.ku...@linux.ibm.com>
> Tested-by: Aneesh Kumar K.V <aneesh.ku...@linux.ibm.com>
> Signed-off-by: Nicholas Piggin <npig...@gmail.com>
> ---
> arch/powerpc/mm/slb.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/powerpc/mm/slb.c b/arch/powerpc/mm/slb.c
> index bc3914d54e26..5986df48359b 100644
> --- a/arch/powerpc/mm/slb.c
> +++ b/arch/powerpc/mm/slb.c
> @@ -69,6 +69,11 @@ static void assert_slb_presence(bool present, unsigned
> long ea)
> if (!cpu_has_feature(CPU_FTR_ARCH_206))
> return;
>
> + /*
> + * slbfee. requires bit 24 (PPC bit 39) be clear in RB. Hardware
> + * ignores all other bits from 0-27, so just clear them all.
> + */
> + ea &= ~((1UL << 28) - 1);
I guess these numbers '28' are derived from the size of the smallest
segment we support. If co can we use ESID_MASK?
> asm volatile(__PPC_SLBFEE_DOT(%0, %1) : "=r"(tmp) : "r"(ea) : "cr0");
>
> WARN_ON(present == (tmp == 0));
> --
> 2.18.0
