On Wed, 2019-02-20 at 01:14 +1100, Michael Ellerman wrote: > Christophe Leroy <christophe.le...@c-s.fr> writes: > > > On 02/08/2019 12:34 PM, Michael Ellerman wrote: > > > In commit 7820856a4fcd ("powerpc/mm/book3e/64: Remove unsupported > > > 64Kpage size from 64bit booke") we dropped the 64K page size support > > > from the 64-bit nohash (Book3E) code. > > > > > > But we didn't update the dependencies of the PPC_64K_PAGES option, > > > meaning a randconfig can still trigger this code and cause a build > > > breakage, eg: > > > arch/powerpc/include/asm/nohash/64/pgtable.h:14:2: error: #error > > > "Page size not supported" > > > arch/powerpc/include/asm/nohash/mmu-book3e.h:275:2: error: #error > > > Unsupported page size > > > > > > So remove PPC_BOOK3E_64 from the dependencies. This also means we > > > don't need to worry about PPC_FSL_BOOK3E, because that was just trying > > > to prevent the PPC_BOOK3E_64=y && PPC_FSL_BOOK3E=y case. > > > > Does it means some cleanup could be done, for instance: > > > > arch/powerpc/include/asm/nohash/64/pgalloc.h:#ifndef CONFIG_PPC_64K_PAGES > > arch/powerpc/include/asm/nohash/64/pgalloc.h:#endif /* > > CONFIG_PPC_64K_PAGES */ > > arch/powerpc/include/asm/nohash/64/pgtable.h:#ifdef CONFIG_PPC_64K_PAGES > > arch/powerpc/include/asm/nohash/64/slice.h:#ifdef CONFIG_PPC_64K_PAGES > > arch/powerpc/include/asm/nohash/64/slice.h:#else /* CONFIG_PPC_64K_PAGES > > */ > > arch/powerpc/include/asm/nohash/64/slice.h:#endif /* > > !CONFIG_PPC_64K_PAGES */ > > arch/powerpc/include/asm/nohash/pte-book3e.h:#ifdef CONFIG_PPC_64K_PAGES > > > > arch/powerpc/mm/tlb_low_64e.S:#ifdef CONFIG_PPC_64K_PAGES > > arch/powerpc/mm/tlb_low_64e.S:#ifndef CONFIG_PPC_64K_PAGES > > arch/powerpc/mm/tlb_low_64e.S:#endif /* CONFIG_PPC_64K_PAGES */ > > arch/powerpc/mm/tlb_low_64e.S:#ifdef CONFIG_PPC_64K_PAGES > > arch/powerpc/mm/tlb_low_64e.S:#ifdef CONFIG_PPC_64K_PAGES > > arch/powerpc/mm/tlb_low_64e.S:#ifndef CONFIG_PPC_64K_PAGES > > arch/powerpc/mm/tlb_low_64e.S:#endif /* CONFIG_PPC_64K_PAGES */ > > arch/powerpc/mm/tlb_low_64e.S:#ifndef CONFIG_PPC_64K_PAGES > > arch/powerpc/mm/tlb_low_64e.S:#endif /* CONFIG_PPC_64K_PAGES */ > > arch/powerpc/mm/tlb_low_64e.S:#ifndef CONFIG_PPC_64K_PAGES > > arch/powerpc/mm/tlb_low_64e.S:#ifdef CONFIG_PPC_64K_PAGES > > Probably. > > Some of the FSL chips do support 64K pages at least according to some > datasheets. I don't know what would be required to get it working, or if > it even works in practice. > > So it would be nice to get 64K working on those chips, but probably no > one has time or motivation to do it. In which case yeah all that code > should be removed.
The primary TLB (TLB0) on these chips only supports 4K pages. TLB1 supports many different sizes but is much smaller, hardware tablewalk only loads into TLB0, etc. -Scott