[PATCH V7 02/14] powerpc/xive: Define xive_native_alloc_get_irq_info()

[Haren Myneni]

pnv_ocxl_alloc_xive_irq() in ocxl.c allocates IRQ and gets trigger port
address. VAS also needs this function, but based on chip ID. So moved
this common function to xive/native.c.

Signed-off-by: Haren Myneni <ha...@linux.ibm.com>
---
 arch/powerpc/include/asm/xive.h       |  2 ++
 arch/powerpc/platforms/powernv/ocxl.c | 20 ++------------------
 arch/powerpc/sysdev/xive/native.c     | 23 +++++++++++++++++++++++
 3 files changed, 27 insertions(+), 18 deletions(-)

diff --git a/arch/powerpc/include/asm/xive.h b/arch/powerpc/include/asm/xive.h
index d08ea11..fd337da 100644
--- a/arch/powerpc/include/asm/xive.h
+++ b/arch/powerpc/include/asm/xive.h
@@ -139,6 +139,8 @@ int xive_native_set_queue_state(u32 vp_id, uint32_t prio, 
u32 qtoggle,
 int xive_native_get_vp_state(u32 vp_id, u64 *out_state);
 bool xive_native_has_queue_state_support(void);
 extern u32 xive_native_alloc_irq_on_chip(u32 chip_id);
+extern int xive_native_alloc_get_irq_info(u32 chip_id, u32 *irq,
+                                       u64 *trigger_addr);
 
 static inline u32 xive_native_alloc_irq(void)
 {
diff --git a/arch/powerpc/platforms/powernv/ocxl.c 
b/arch/powerpc/platforms/powernv/ocxl.c
index 8c65aac..fb8f99a 100644
--- a/arch/powerpc/platforms/powernv/ocxl.c
+++ b/arch/powerpc/platforms/powernv/ocxl.c
@@ -487,24 +487,8 @@ int pnv_ocxl_spa_remove_pe_from_cache(void *platform_data, 
int pe_handle)
 
 int pnv_ocxl_alloc_xive_irq(u32 *irq, u64 *trigger_addr)
 {
-       __be64 flags, trigger_page;
-       s64 rc;
-       u32 hwirq;
-
-       hwirq = xive_native_alloc_irq();
-       if (!hwirq)
-               return -ENOENT;
-
-       rc = opal_xive_get_irq_info(hwirq, &flags, NULL, &trigger_page, NULL,
-                               NULL);
-       if (rc || !trigger_page) {
-               xive_native_free_irq(hwirq);
-               return -ENOENT;
-       }
-       *irq = hwirq;
-       *trigger_addr = be64_to_cpu(trigger_page);
-       return 0;
-
+       return xive_native_alloc_get_irq_info(OPAL_XIVE_ANY_CHIP, irq,
+                                               trigger_addr);
 }
 EXPORT_SYMBOL_GPL(pnv_ocxl_alloc_xive_irq);
 
diff --git a/arch/powerpc/sysdev/xive/native.c 
b/arch/powerpc/sysdev/xive/native.c
index 14d4406..abdd892 100644
--- a/arch/powerpc/sysdev/xive/native.c
+++ b/arch/powerpc/sysdev/xive/native.c
@@ -295,6 +295,29 @@ u32 xive_native_alloc_irq_on_chip(u32 chip_id)
 }
 EXPORT_SYMBOL_GPL(xive_native_alloc_irq_on_chip);
 
+int xive_native_alloc_get_irq_info(u32 chip_id, u32 *irq, u64 *trigger_addr)
+{
+       __be64 flags, trigger_page;
+       u32 hwirq;
+       s64 rc;
+
+       hwirq = xive_native_alloc_irq_on_chip(chip_id);
+       if (!hwirq)
+               return -ENOENT;
+
+       rc = opal_xive_get_irq_info(hwirq, &flags, NULL, &trigger_page, NULL,
+                               NULL);
+       if (rc || !trigger_page) {
+               xive_native_free_irq(hwirq);
+               return -ENOENT;
+       }
+       *irq = hwirq;
+       *trigger_addr = be64_to_cpu(trigger_page);
+
+       return 0;
+}
+EXPORT_SYMBOL(xive_native_alloc_get_irq_info);
+
 void xive_native_free_irq(u32 irq)
 {
        for (;;) {
-- 
1.8.3.1