Jordan Niethe's on March 20, 2020 3:18 pm: > From: Alistair Popple <alist...@popple.id.au> > > Prefix instructions have their own FSCR bit which needs to enabled via > a CPU feature. The kernel will save the FSCR for problem state but it > needs to be enabled initially. > > If prefixed instructions are made unavailable by the [H]FSCR, attempting > to use them will cause a facility unavailable exception. Add "PREFIX" to > the facility_strings[]. > > Currently there are no prefixed instructions that are actually emulated > by emulate_instruction() within facility_unavailable_exception(). > However, when caused by a prefixed instructions the SRR1 PREFIXED bit is > set. Prepare for dealing with emulated prefixed instructions by checking > for this bit. >
Reviewed-by: Nicholas Piggin <npig...@gmail.com> > Signed-off-by: Alistair Popple <alist...@popple.id.au> > Signed-off-by: Jordan Niethe <jniet...@gmail.com> > --- > v4: > - Squash "Check for prefixed instructions in > facility_unavailable_exception()" here > - Remove dt parts for now > --- > arch/powerpc/include/asm/reg.h | 3 +++ > arch/powerpc/kernel/traps.c | 1 + > 2 files changed, 4 insertions(+) > > diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h > index 1aa46dff0957..c7758c2ccc5f 100644 > --- a/arch/powerpc/include/asm/reg.h > +++ b/arch/powerpc/include/asm/reg.h > @@ -397,6 +397,7 @@ > #define SPRN_RWMR 0x375 /* Region-Weighting Mode Register */ > > /* HFSCR and FSCR bit numbers are the same */ > +#define FSCR_PREFIX_LG 13 /* Enable Prefix Instructions */ > #define FSCR_SCV_LG 12 /* Enable System Call Vectored */ > #define FSCR_MSGP_LG 10 /* Enable MSGP */ > #define FSCR_TAR_LG 8 /* Enable Target Address Register */ > @@ -408,11 +409,13 @@ > #define FSCR_VECVSX_LG 1 /* Enable VMX/VSX */ > #define FSCR_FP_LG 0 /* Enable Floating Point */ > #define SPRN_FSCR 0x099 /* Facility Status & Control Register */ > +#define FSCR_PREFIX __MASK(FSCR_PREFIX_LG) > #define FSCR_SCV __MASK(FSCR_SCV_LG) > #define FSCR_TAR __MASK(FSCR_TAR_LG) > #define FSCR_EBB __MASK(FSCR_EBB_LG) > #define FSCR_DSCR __MASK(FSCR_DSCR_LG) > #define SPRN_HFSCR 0xbe /* HV=1 Facility Status & Control Register */ > +#define HFSCR_PREFIX __MASK(FSCR_PREFIX_LG) > #define HFSCR_MSGP __MASK(FSCR_MSGP_LG) > #define HFSCR_TAR __MASK(FSCR_TAR_LG) > #define HFSCR_EBB __MASK(FSCR_EBB_LG) > diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c > index 82a3438300fd..a4764b039749 100644 > --- a/arch/powerpc/kernel/traps.c > +++ b/arch/powerpc/kernel/traps.c > @@ -1720,6 +1720,7 @@ void facility_unavailable_exception(struct pt_regs > *regs) > [FSCR_TAR_LG] = "TAR", > [FSCR_MSGP_LG] = "MSGP", > [FSCR_SCV_LG] = "SCV", > + [FSCR_PREFIX_LG] = "PREFIX", > }; > char *facility = "unknown"; > u64 value; > -- > 2.17.1 > >
