On Mon, Mar 23, 2020 at 07:58:01PM +1100, Alexey Kardashevskiy wrote: > >> 0x100.0000.0000 .. 0x101.0000.0000 > >> > >> 2x4G, each is 1TB aligned. And we can map directly only the first 4GB > >> (because of the maximum IOMMU table size) but not the other. And 1:1 on > >> that "pseries" is done with offset=0x0800.0000.0000.0000. > >> > >> So we want to check every bus address against dev->bus_dma_limit, not > >> dev->coherent_dma_mask. In the example above I'd set bus_dma_limit to > >> 0x0800.0001.0000.0000 and 1:1 mapping for the second 4GB would not be > >> tried. Does this sound reasonable? Thanks, > > > > bus_dma_limit is just another limiting factor applied on top of > > coherent_dma_mask or dma_mask respectively. > > This is not enough for the task: in my example, I'd set bus limit to > 0x0800.0001.0000.0000 but this would disable bypass for all RAM > addresses - the first and the second 4GB blocks.
So what about something like the version here: http://git.infradead.org/users/hch/misc.git/shortlog/refs/heads/dma-bypass.3
