On 3/19/20 7:12 AM, Haren Myneni wrote:
>
> This function allocates IRQ on a specific chip. VAS needs per chip
> IRQ allocation and will have IRQ handler per VAS instance.
>
> Signed-off-by: Haren Myneni <ha...@linux.ibm.com>
Reviewed-by: Cédric Le Goater <c...@kaod.org>
Thanks,
C.
> ---
> arch/powerpc/include/asm/xive.h | 9 ++++++++-
> arch/powerpc/sysdev/xive/native.c | 6 +++---
> 2 files changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/xive.h b/arch/powerpc/include/asm/xive.h
> index 93f982db..d08ea11 100644
> --- a/arch/powerpc/include/asm/xive.h
> +++ b/arch/powerpc/include/asm/xive.h
> @@ -5,6 +5,8 @@
> #ifndef _ASM_POWERPC_XIVE_H
> #define _ASM_POWERPC_XIVE_H
>
> +#include <asm/opal-api.h>
> +
> #define XIVE_INVALID_VP 0xffffffff
>
> #ifdef CONFIG_PPC_XIVE
> @@ -108,7 +110,6 @@ struct xive_q {
> int xive_native_populate_irq_data(u32 hw_irq,
> struct xive_irq_data *data);
> void xive_cleanup_irq_data(struct xive_irq_data *xd);
> -u32 xive_native_alloc_irq(void);
> void xive_native_free_irq(u32 irq);
> int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq);
>
> @@ -137,6 +138,12 @@ int xive_native_set_queue_state(u32 vp_id, uint32_t
> prio, u32 qtoggle,
> u32 qindex);
> int xive_native_get_vp_state(u32 vp_id, u64 *out_state);
> bool xive_native_has_queue_state_support(void);
> +extern u32 xive_native_alloc_irq_on_chip(u32 chip_id);
> +
> +static inline u32 xive_native_alloc_irq(void)
> +{
> + return xive_native_alloc_irq_on_chip(OPAL_XIVE_ANY_CHIP);
> +}
>
> #else
>
> diff --git a/arch/powerpc/sysdev/xive/native.c
> b/arch/powerpc/sysdev/xive/native.c
> index 0ff6b73..14d4406 100644
> --- a/arch/powerpc/sysdev/xive/native.c
> +++ b/arch/powerpc/sysdev/xive/native.c
> @@ -279,12 +279,12 @@ static int xive_native_get_ipi(unsigned int cpu, struct
> xive_cpu *xc)
> }
> #endif /* CONFIG_SMP */
>
> -u32 xive_native_alloc_irq(void)
> +u32 xive_native_alloc_irq_on_chip(u32 chip_id)
> {
> s64 rc;
>
> for (;;) {
> - rc = opal_xive_allocate_irq(OPAL_XIVE_ANY_CHIP);
> + rc = opal_xive_allocate_irq(chip_id);
> if (rc != OPAL_BUSY)
> break;
> msleep(OPAL_BUSY_DELAY_MS);
> @@ -293,7 +293,7 @@ u32 xive_native_alloc_irq(void)
> return 0;
> return rc;
> }
> -EXPORT_SYMBOL_GPL(xive_native_alloc_irq);
> +EXPORT_SYMBOL_GPL(xive_native_alloc_irq_on_chip);
>
> void xive_native_free_irq(u32 irq)
> {
>
