Hi mpe, Could you please take some changes for the commit message. In the patch title s/a future ISA version/ISA v3.1/
On Wed, May 6, 2020 at 1:47 PM Jordan Niethe <jniet...@gmail.com> wrote: > > Add the BOUNDARY SRR1 bit definition for when the cause of an alignment > exception is a prefixed instruction that crosses a 64-byte boundary. > Add the PREFIXED SRR1 bit definition for exceptions caused by prefixed > instructions. > > Bit 35 of SRR1 is called SRR1_ISI_N_OR_G. This name comes from it being > used to indicate that an ISI was due to the access being no-exec or > guarded. A future ISA version adds another purpose. It is also set if s/A future ISA version/ISA v3.1/ > there is an access in a cache-inhibited location for prefixed > instruction. Rename from SRR1_ISI_N_OR_G to SRR1_ISI_N_G_OR_CIP. > > Reviewed-by: Alistair Popple <alist...@popple.id.au> > Signed-off-by: Jordan Niethe <jniet...@gmail.com> > --- > v2: Combined all the commits concerning SRR1 bits. > ---