Excerpts from Christophe Leroy's message of July 6, 2020 7:53 pm: > > > Le 06/07/2020 à 04:18, Nicholas Piggin a écrit : >> diff --git a/arch/powerpc/include/asm/exception-64s.h >> b/arch/powerpc/include/asm/exception-64s.h >> index 47bd4ea0837d..b88cb3a989b6 100644 >> --- a/arch/powerpc/include/asm/exception-64s.h >> +++ b/arch/powerpc/include/asm/exception-64s.h >> @@ -68,6 +68,10 @@ >> * >> * The nop instructions allow us to insert one or more instructions to >> flush the >> * L1-D cache when returning to userspace or a guest. >> + * >> + * powerpc relies on return from interrupt/syscall being context >> synchronising >> + * (which hrfid, rfid, and rfscv are) to support >> ARCH_HAS_MEMBARRIER_SYNC_CORE >> + * without additional additional synchronisation instructions. > > This file is dedicated to BOOK3S/64. What about other ones ? > > On 32 bits, this is also valid as 'rfi' is also context synchronising, > but then why just add some comment in exception-64s.h and only there ?
Yeah you're right, I basically wanted to keep a note there just in case, because it's possible we would get a less synchronising return (maybe unlikely with meltdown) or even return from a kernel interrupt using a something faster (e.g., bctar if we don't use tar register in the kernel anywhere). So I wonder where to add the note, entry_32.S and 64e.h as well? I should actually change the comment for 64-bit because soft masked interrupt replay is an interesting case. I thought it was okay (because the IPI would cause a hard interrupt which does do the rfi) but that should at least be written. The context synchronisation happens before the Linux IPI function is called, but for the purpose of membarrier I think that is okay (the membarrier just needs to have caused a memory barrier + context synchronistaion by the time it has done). Thanks, Nick