On Wed, 1 Jul 2020 12:52:28 +0530, Aneesh Kumar K.V wrote:
> This patch series enables the usage os new pmem flush and sync instructions 
> on POWER
> architecture. POWER10 introduces two new variants of dcbf instructions 
> (dcbstps and dcbfps)
> that can be used to write modified locations back to persistent storage. 
> Additionally,
> POWER10 also introduce phwsync and plwsync which can be used to establish 
> order of these
> writes to persistent storage.
> This series exposes these instructions to the rest of the kernel. The existing
> dcbf and hwsync instructions in P8 and P9 are adequate to enable appropriate
> synchronization with OpenCAPI-hosted persistent storage. Hence the new 
> instructions
> are added as a variant of the old ones that old hardware won't differentiate.
> [...]

Applied to powerpc/next.

[1/7] powerpc/pmem: Restrict papr_scm to P8 and above.
[2/7] powerpc/pmem: Add new instructions for persistent storage and sync
[3/7] powerpc/pmem: Add flush routines using new pmem store and sync instruction
[4/7] libnvdimm/nvdimm/flush: Allow architecture to override the flush barrier
[5/7] powerpc/pmem: Update ppc64 to use the new barrier instruction.
[6/7] powerpc/pmem: Avoid the barrier in flush routines
[7/7] powerpc/pmem: Initialize pmem device on newer hardware


Reply via email to