> On 24-Jul-2020, at 8:32 AM, kernel test robot <l...@intel.com> wrote:
>
> Hi Athira,
>
> Thank you for the patch! Yet something to improve:
>
> [auto build test ERROR on powerpc/next]
> [also build test ERROR on v5.8-rc6 next-20200723]
> [cannot apply to mpe/next scottwood/next]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch]
>
> url:
> https://github.com/0day-ci/linux/commits/Athira-Rajeev/powerpc-perf-Initialize-power10-PMU-registers-in-cpu-setup-routine/20200723-153537
> base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
> config: powerpc-defconfig (attached as .config)
> compiler: powerpc64-linux-gcc (GCC) 9.3.0
> reproduce (this is a W=1 build):
> wget
> https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
> ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # save the attached .config to linux build tree
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross
> ARCH=powerpc
>
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <l...@intel.com>
>
> All errors (new ones prefixed by >>):
>
> arch/powerpc/kernel/cpu_setup_power.S: Assembler messages:
>>> arch/powerpc/kernel/cpu_setup_power.S:244: Error: non-constant expression
>>> in ".if" statement
>>> arch/powerpc/kernel/cpu_setup_power.S:244: Error: non-constant expression
>>> in ".if" statement
>>> arch/powerpc/kernel/cpu_setup_power.S:243: Error: unsupported relocation
>>> against SPRN_MMCR3
Hi,
As mentioned in changelog:
This patch was initially part of Power10 PMU base enablement
series ( https://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=190462
).
Moving this as separate patch as suggested by Michael
Ellerman. Hence there is a dependency on initial series ( Patch 7 ) which
defines
MMCRA_BHRB_DISABLE and new SPR’s. And the build error is because of that.
Thanks
Athira
>
> vim +244 arch/powerpc/kernel/cpu_setup_power.S
>
> 14
> 15 /* Entry: r3 = crap, r4 = ptr to cputable entry
> 16 *
> 17 * Note that we can be called twice for pseudo-PVRs
> 18 */
> 19 _GLOBAL(__setup_cpu_power7)
> 20 mflr r11
> 21 bl __init_hvmode_206
> 22 mtlr r11
> 23 beqlr
> 24 li r0,0
> 25 mtspr SPRN_LPID,r0
> 26 LOAD_REG_IMMEDIATE(r0, PCR_MASK)
> 27 mtspr SPRN_PCR,r0
> 28 mfspr r3,SPRN_LPCR
> 29 li r4,(LPCR_LPES1 >> LPCR_LPES_SH)
> 30 bl __init_LPCR_ISA206
> 31 mtlr r11
> 32 blr
> 33
> 34 _GLOBAL(__restore_cpu_power7)
> 35 mflr r11
> 36 mfmsr r3
> 37 rldicl. r0,r3,4,63
> 38 beqlr
> 39 li r0,0
> 40 mtspr SPRN_LPID,r0
> 41 LOAD_REG_IMMEDIATE(r0, PCR_MASK)
> 42 mtspr SPRN_PCR,r0
> 43 mfspr r3,SPRN_LPCR
> 44 li r4,(LPCR_LPES1 >> LPCR_LPES_SH)
> 45 bl __init_LPCR_ISA206
> 46 mtlr r11
> 47 blr
> 48
> 49 _GLOBAL(__setup_cpu_power8)
> 50 mflr r11
> 51 bl __init_FSCR
> 52 bl __init_PMU
> 53 bl __init_PMU_ISA207
> 54 bl __init_hvmode_206
> 55 mtlr r11
> 56 beqlr
> 57 li r0,0
> 58 mtspr SPRN_LPID,r0
> 59 LOAD_REG_IMMEDIATE(r0, PCR_MASK)
> 60 mtspr SPRN_PCR,r0
> 61 mfspr r3,SPRN_LPCR
> 62 ori r3, r3, LPCR_PECEDH
> 63 li r4,0 /* LPES = 0 */
> 64 bl __init_LPCR_ISA206
> 65 bl __init_HFSCR
> 66 bl __init_PMU_HV
> 67 bl __init_PMU_HV_ISA207
> 68 mtlr r11
> 69 blr
> 70
> 71 _GLOBAL(__restore_cpu_power8)
> 72 mflr r11
> 73 bl __init_FSCR
> 74 bl __init_PMU
> 75 bl __init_PMU_ISA207
> 76 mfmsr r3
> 77 rldicl. r0,r3,4,63
> 78 mtlr r11
> 79 beqlr
> 80 li r0,0
> 81 mtspr SPRN_LPID,r0
> 82 LOAD_REG_IMMEDIATE(r0, PCR_MASK)
> 83 mtspr SPRN_PCR,r0
> 84 mfspr r3,SPRN_LPCR
> 85 ori r3, r3, LPCR_PECEDH
> 86 li r4,0 /* LPES = 0 */
> 87 bl __init_LPCR_ISA206
> 88 bl __init_HFSCR
> 89 bl __init_PMU_HV
> 90 bl __init_PMU_HV_ISA207
> 91 mtlr r11
> 92 blr
> 93
> 94 _GLOBAL(__setup_cpu_power10)
> 95 mflr r11
> 96 bl __init_FSCR_power10
> 97 bl __init_PMU
> 98 bl __init_PMU_ISA31
> 99 b 1f
> 100
> 101 _GLOBAL(__setup_cpu_power9)
> 102 mflr r11
> 103 bl __init_FSCR
> 104 bl __init_PMU
> 105 1: bl __init_hvmode_206
> 106 mtlr r11
> 107 beqlr
> 108 li r0,0
> 109 mtspr SPRN_PSSCR,r0
> 110 mtspr SPRN_LPID,r0
> 111 mtspr SPRN_PID,r0
> 112 LOAD_REG_IMMEDIATE(r0, PCR_MASK)
> 113 mtspr SPRN_PCR,r0
> 114 mfspr r3,SPRN_LPCR
> 115 LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE |
> LPCR_HVICE | LPCR_HEIC)
> 116 or r3, r3, r4
> 117 LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
> 118 andc r3, r3, r4
> 119 li r4,0 /* LPES = 0 */
> 120 bl __init_LPCR_ISA300
> 121 bl __init_HFSCR
> 122 bl __init_PMU_HV
> 123 mtlr r11
> 124 blr
> 125
> 126 _GLOBAL(__restore_cpu_power10)
> 127 mflr r11
> 128 bl __init_FSCR_power10
> 129 bl __init_PMU
> 130 bl __init_PMU_ISA31
> 131 b 1f
> 132
> 133 _GLOBAL(__restore_cpu_power9)
> 134 mflr r11
> 135 bl __init_FSCR
> 136 bl __init_PMU
> 137 1: mfmsr r3
> 138 rldicl. r0,r3,4,63
> 139 mtlr r11
> 140 beqlr
> 141 li r0,0
> 142 mtspr SPRN_PSSCR,r0
> 143 mtspr SPRN_LPID,r0
> 144 mtspr SPRN_PID,r0
> 145 LOAD_REG_IMMEDIATE(r0, PCR_MASK)
> 146 mtspr SPRN_PCR,r0
> 147 mfspr r3,SPRN_LPCR
> 148 LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE |
> LPCR_HVICE | LPCR_HEIC)
> 149 or r3, r3, r4
> 150 LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
> 151 andc r3, r3, r4
> 152 li r4,0 /* LPES = 0 */
> 153 bl __init_LPCR_ISA300
> 154 bl __init_HFSCR
> 155 bl __init_PMU_HV
> 156 mtlr r11
> 157 blr
> 158
> 159 __init_hvmode_206:
> 160 /* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
> 161 mfmsr r3
> 162 rldicl. r0,r3,4,63
> 163 bnelr
> 164 ld r5,CPU_SPEC_FEATURES(r4)
> 165 LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE | CPU_FTR_P9_TM_HV_ASSIST)
> 166 andc r5,r5,r6
> 167 std r5,CPU_SPEC_FEATURES(r4)
> 168 blr
> 169
> 170 __init_LPCR_ISA206:
> 171 /* Setup a sane LPCR:
> 172 * Called with initial LPCR in R3 and desired LPES 2-bit
> value in R4
> 173 *
> 174 * LPES = 0b01 (HSRR0/1 used for 0x500)
> 175 * PECE = 0b111
> 176 * DPFD = 4
> 177 * HDICE = 0
> 178 * VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
> 179 * VRMASD = 0b10000 (L=1, LP=00)
> 180 *
> 181 * Other bits untouched for now
> 182 */
> 183 li r5,0x10
> 184 rldimi r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
> 185
> 186 /* POWER9 has no VRMASD */
> 187 __init_LPCR_ISA300:
> 188 rldimi r3,r4, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
> 189 ori r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
> 190 li r5,4
> 191 rldimi r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
> 192 clrrdi r3,r3,1 /* clear HDICE */
> 193 li r5,4
> 194 rldimi r3,r5, LPCR_VC_SH, 0
> 195 mtspr SPRN_LPCR,r3
> 196 isync
> 197 blr
> 198
> 199 __init_FSCR_power10:
> 200 mfspr r3, SPRN_FSCR
> 201 ori r3, r3, FSCR_PREFIX
> 202 mtspr SPRN_FSCR, r3
> 203 // fall through
> 204
> 205 __init_FSCR:
> 206 mfspr r3,SPRN_FSCR
> 207 ori r3,r3,FSCR_TAR|FSCR_EBB
> 208 mtspr SPRN_FSCR,r3
> 209 blr
> 210
> 211 __init_HFSCR:
> 212 mfspr r3,SPRN_HFSCR
> 213 ori r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|\
> 214
> HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB|HFSCR_MSGP
> 215 mtspr SPRN_HFSCR,r3
> 216 blr
> 217
> 218 __init_PMU_HV:
> 219 li r5,0
> 220 mtspr SPRN_MMCRC,r5
> 221 blr
> 222
> 223 __init_PMU_HV_ISA207:
> 224 li r5,0
> 225 mtspr SPRN_MMCRH,r5
> 226 blr
> 227
> 228 __init_PMU:
> 229 li r5,0
> 230 mtspr SPRN_MMCRA,r5
> 231 mtspr SPRN_MMCR0,r5
> 232 mtspr SPRN_MMCR1,r5
> 233 mtspr SPRN_MMCR2,r5
> 234 blr
> 235
> 236 __init_PMU_ISA207:
> 237 li r5,0
> 238 mtspr SPRN_MMCRS,r5
> 239 blr
> 240
> 241 __init_PMU_ISA31:
> 242 li r5,0
>> 243 mtspr SPRN_MMCR3,r5
>> 244 LOAD_REG_IMMEDIATE(r5, MMCRA_BHRB_DISABLE)
>
> ---
> 0-DAY CI Kernel Test Service, Intel Corporation
> https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
> <.config.gz>
