Hi Christophe,

+static int cache_op_size(void)
+#ifdef __powerpc64__
+    return ppc64_caches.l1d.block_size;
+    return L1_CACHE_BYTES;

You've got l1_dcache_bytes() in arch/powerpc/include/asm/cache.h to do that.

+void wp_get_instr_detail(struct pt_regs *regs, struct ppc_inst *instr,
+             int *type, int *size, unsigned long *ea)
+    struct instruction_op op;
+    if (__get_user_instr_inatomic(*instr, (void __user *)regs->nip))
+        return;
+    analyse_instr(&op, regs, *instr);
+    *type = GETTYPE(op.type);
+    *ea = op.ea;
+#ifdef __powerpc64__
+    if (!(regs->msr & MSR_64BIT))
+        *ea &= 0xffffffffUL;

This #ifdef is unneeded, it should build fine on a 32 bits too.

This patch is just a code movement from one file to another.
I don't really change the logic. Would you mind if I do a
separate patch for these changes (not a part of this series)?

Thanks for review,

Reply via email to