Hi Anton, > The mpc8xxx_wdt driver is using two registers: SWSRR to push magic > numbers, and SWCRR to control the watchdog. Both registers are available > on the MPC8xx, and seem to have the same offsets and semantics as in > MPC83xx/MPC86xx watchdogs. The only difference is prescale value. So this > driver should simply work on the MPC8xx CPUs. > > MPC823 seem to be the first CPU in MPC8xx line, so we use fsl,mpc823-wdt > compatible matching. > > Though, this patch was only build-tested and okay to drop from this > series until tested or corrected to work on the actual hardware. > > Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
Tested-by: Jochen Friedrich <[EMAIL PROTECTED]> The driver works OK on MPC823. One nit however ist the late initialisation of the wdt timer. I had to add two hardcoded wdt resets in the board setup, one in setup_arch and one in arch_initcall, to prevent a reset until mpc8xxx_wdt kicks in. However, IMHO this is acceptable as it only hits the 8xx series with the small prescale. Some time ago in http://patchwork.ozlabs.org/linuxppc/patch?person=1023&id=16189, i tried a different aproach to the problem (mainly a port of the old ARC=ppc stuff), but the code became very ugly and the wdt maintainers didn't like it very much. So the only thing left for full 8xx support is a refactoring / cleanup of http://patchwork.ozlabs.org/linuxppc/patch?person=1023&id=16262. Thanks, Jochen _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
