Excerpts from Christophe Leroy's message of November 10, 2020 9:31 pm: > > > Le 10/11/2020 à 09:49, Nicholas Piggin a écrit : >> Excerpts from Christophe Leroy's message of November 7, 2020 8:35 pm: >>> >>> >>> Le 06/11/2020 à 16:59, Nicholas Piggin a écrit : >>>> This series attempts to improve the speed of interrupts and system calls >>>> in two major ways. >>>> >>>> Firstly, the SRR/HSRR registers do not need to be reloaded if they were >>>> not used or clobbered fur the duration of the interrupt. >>>> >>>> Secondly, an alternate return location facility is added for soft-masked >>>> asynchronous interrupts and then that's used to set everything up for >>>> return without having to disable MSR RI or EE. >>>> >>>> After this series, the entire system call / interrupt handler fast path >>>> executes no mtsprs and one mtmsrd to enable interrupts initially, and >>>> the system call vectored path doesn't even need to do that. >>> >>> Interesting series. >>> >>> Unfortunately, can't be done on PPC32 (at least on non bookE), because it >>> would mean mapping kernel >>> at 0 instead of 0xC0000000. Not sure libc would like it, and anyway it >>> would be an issue for >>> catching NULL pointer dereferencing, unless we use page tables instead of >>> BATs to map kernel mem, >>> which would be serious performance cut. >> >> Hmm, why would you have to map at 0? > > In real mode, physical mem is at 0. If we want to switch from real to virtual > mode by just writing > to MSR, then we need virtuel addresses match with real addresses ?
Ah that's what I missed. 64s real mode masks out the top 2 bits of the address which is how that works. But I don't usually think about that path anyway because most iterrupts arrive with MMU on. > We could play with chip selects to put RAM at 0xc0000000, but then we'd have > a problem with > exception as they have to be at 0. Or we could play with MSR[IP] and get the > exceptions at > 0xfff00000, but that would not be so easy I guess. > >> >> PPC32 doesn't have soft mask interrupts, but you could still test all >> MSR[PR]=0 interrupts to see if they land inside some region to see if >> they hit in the restart table I think? > > Yes and this is already what is done at exit for the ones that handle MSR[RI] > I think. Interesting, I'll have to check that out. >> >> Could PPC32 skip the SRR reload at least? That's simpler. > > I think that would only be possible if real addresses where matching virtual > addresses, or am I > missing something ? No you're right, I was missing something. Thanks, Nick