On Fri, 7 May 2021 05:02:02 +0000 (UTC), Christophe Leroy wrote: > The SW LRU is in an MMU feature section. When not used, that's a > dozen of NOPs to fetch for nothing. > > Define an ALT section that does the few remaining operations. > > That also avoids a double read on SRR1 in the SW LRU case.
Applied to powerpc/next. [1/1] powerpc/603: Avoid a pile of NOPs when not using SW LRU in TLB exceptions https://git.kernel.org/powerpc/c/70d6ebf82bd0cfddaebb54e861fc15e9945a5fc6 cheers