Le 23/08/2021 à 17:58, Segher Boessenkool a écrit :
On Mon, Aug 23, 2021 at 07:53:01AM +0000, Christophe Leroy wrote:
/* Be careful, this will clobber the lr register. */
#define LOAD_REG_ADDR_PIC(reg, name) \
- bl 0f; \
+ bcl 20,31,0f \
0: mflr reg; \
addis reg,reg,(name - 0b)@ha; \
addi reg,reg,(name - 0b)@l;
The code ended each line with a semicolon before, for absolutely no
reason that I can see, but still. Fixing that would be nice, but only
doing it on one line isn't good.
Sure, forgetting the semicolon broke the build. That's because the backslash
removes the newline.
The cleanest way I found to fix that quite of stuff is by using GAS macro, as I did for
LOAD_REG_IMMEDIATE() some time ago.
Btw. Both the 7450 and the modern cores implementing this really need
this to be $+4, so it is a lot clearer to write that instead of 1f or
a named label.
I like that, removing unneeded labels will make it smoother and clearer. I'll
do it.
Christophe
