Christophe Leroy <christophe.le...@csgroup.eu> writes:
> HMT_xxx macros are macros for adjusting thread priority
> (hardware multi-threading) are macros inherited from PPC64
> via commit 5f7c690728ac ("[PATCH] powerpc: Merged ppc_asm.h")
>
> Those instructions are pointless on PPC32, but some common
> fonctions like arch_cpu_idle() use them.
>
> So make them empty on PPC32 to avoid those instructions.
I guess we're pretty sure no 32-bit CPUs do anything with those.
e6500 can run in 32-bit mode, and is 2-way threaded AIUI, so it's
*possible* it could use them.
But I can't find any mention of those special nops in the e6500 core
manual. And actually it does have documentation about thread priority
registers, PPR32, TPRI0/1, but it says they're not used in e6500.
So I guess this seems safe, I'll pick it up.
cheers
> diff --git a/arch/powerpc/include/asm/vdso/processor.h
> b/arch/powerpc/include/asm/vdso/processor.h
> index e072577bc7c0..8d79f994b4aa 100644
> --- a/arch/powerpc/include/asm/vdso/processor.h
> +++ b/arch/powerpc/include/asm/vdso/processor.h
> @@ -5,12 +5,21 @@
> #ifndef __ASSEMBLY__
>
> /* Macros for adjusting thread priority (hardware multi-threading) */
> +#ifdef CONFIG_PPC64
> #define HMT_very_low() asm volatile("or 31, 31, 31 # very
> low priority")
> #define HMT_low() asm volatile("or 1, 1, 1 # low priority")
> #define HMT_medium_low() asm volatile("or 6, 6, 6 # medium low
> priority")
> #define HMT_medium() asm volatile("or 2, 2, 2 # medium
> priority")
> #define HMT_medium_high() asm volatile("or 5, 5, 5 # medium high
> priority")
> #define HMT_high() asm volatile("or 3, 3, 3 # high
> priority")
> +#else
> +#define HMT_very_low()
> +#define HMT_low()
> +#define HMT_medium_low()
> +#define HMT_medium()
> +#define HMT_medium_high()
> +#define HMT_high()
> +#endif
>
> #ifdef CONFIG_PPC64
> #define cpu_relax() do { HMT_low(); HMT_medium(); barrier(); } while (0)
> --
> 2.25.0
